Paper Title:
Enhanced Channel Mobility in 4H-SiC MISFETs by Utilizing Deposited SiN/SiO2 Stack Gate Structures
  Abstract

Deposited SiN/SiO2 stack gate structures have been investigated to improve the 4H-SiC MOS interface quality. Capacitance-voltage measurements on fabricated SiN/SiO2 stack gate MIS capacitors have indicated that the interface state density is reduced by post-deposition annealing in N2O at 1300°C. The usage of thin SiN and increase in N2O-annealing time lead to a low interface state density of 1×1011 cm-2eV-1 at EC – 0.2 eV. Oxidation of the SiN during N2O annealing has resulted in improvement of SiC MIS interface. The fabricated SiN/SiO2 stack gate MISFETs demonstrate a high channel mobility of 32 cm2/Vs on (0001)Si face and 40 cm2/Vs on (000-1)C face.

  Info
Periodical
Materials Science Forum (Volumes 600-603)
Edited by
Akira Suzuki, Hajime Okumura, Tsunenobu Kimoto, Takashi Fuyuki, Kenji Fukuda and Shin-ichi Nishizawa
Pages
679-682
DOI
10.4028/www.scientific.net/MSF.600-603.679
Citation
M. Noborio, J. Suda, T. Kimoto, "Enhanced Channel Mobility in 4H-SiC MISFETs by Utilizing Deposited SiN/SiO2 Stack Gate Structures ", Materials Science Forum, Vols. 600-603, pp. 679-682, 2009
Online since
September 2008
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