Complementary lateral structures, N-JFETs, P-JFETS and bipolar diodes, have been implemented in p and n-type 4H-SiC wafers with epilayers. The device were optimized using finite element code MEDICITM simulations, based on ion implanted and etched Reduced-Surface-Field structures. Two Ti/Ni alloy composition are found to form ohmic contacts compatibles with high temperature device operation. 900°C and respectively 1000°C post-metallisation annealing during 2min are necessary. The presence of a graphite layer is determined by XPS (X-ray photon spectroscopy) analyses at the metal-semiconductor interface. On the fabricated p and n-type lateral JFETs, in blocking state, breakdown voltage as high as 600V are obtained.