Characterization of Phosphorus Implanted n+/p Junctions Integrated as Source/Drain Regions in a 4H-SiC n-MOSFET
| Periodical | Materials Science Forum (Volumes 615 - 617) |
|---|---|
| Main Theme | Silicon Carbide and Related Materials 2008 |
| Edited by | Amador Pérez-Tomás, Philippe Godignon, Miquel Vellvehí and Pierre Brosselard |
| Pages | 687-690 |
| DOI | 10.4028/www.scientific.net/MSF.615-617.687 |
| Citation | Francesco Moscatelli et al., 2009, Materials Science Forum, 615-617, 687 |
| Online since | March, 2009 |
| Authors | Francesco Moscatelli, Roberta Nipoti, Antonella Poggi, Sandro Solmi, Stefano Cristiani, Michele Sanmartin |
| Keywords | Annealing, n+/p Junction, Phosphorus Ion Implantation, Surface Passivation |
| Price | US$ 28,- |
Phosphorous implanted n+/p diodes have been included in the masks for manufacturing n-MOSFET devices and processed in the same way of source/drain regions. The diode junctions were made by a P+ implantation at 300°C and a post implantation annealing at 1300°C. The diode emitter area was protected by 0.6 m thick CVD oxide during the processing of the MOSFET gate oxide. Three gate oxide processes were taken into account: two of them include a N implantation before a wet oxidation, while the third one was a standard oxidation. Considering the effect on the n+/p diodes, the main difference among the processes were the wet thermal oxidation time that ranged between 180 and 480 min at a temperature of 1100°C. The diode current-voltage characteristics show similar forward but different reverse curves in the temperature range of 25-290°C. Differences in reverse bias voltage as a function of the measurement temperature have been analyzed and are related to the different gate oxidation time. A correlation between the shortest oxidation time and the lower leakage current is presented.
