Paper Title:
1.5 kV Lateral Double RESURF MOSFETs on 4H-SiC (000-1)C Face
  Abstract

SiC lateral double RESURF MOSFETs have been fabricated on the 4H-SiC (000-1)C face. By utilizing the C face, the channel resistance can be reduced because the C-face MOSFETs show higher channel mobility than the Si-face MOSFETs. In addition, by employing the double RESURF structure, the drift resistance is decreased and the breakdown voltage is increased with increasing the RESURF doses. The fabricated RESURF MOSFETs on the 4H-SiC (000-1)C face have demonstrated a low on-resistance of 40 mΩcm2 at an oxide field of 3 MV/cm and a breakdown voltage of 1580 V at zero gate bias. The figure-of-merit of the MOSFET is 62 MW/cm2, which is more than 10 times better than the conventional “Si limit” and the highest value among any lateral MOSFETs to date.

  Info
Periodical
Materials Science Forum (Volumes 615-617)
Edited by
Amador Pérez-Tomás, Philippe Godignon, Miquel Vellvehí and Pierre Brosselard
Pages
757-760
DOI
10.4028/www.scientific.net/MSF.615-617.757
Citation
M. Noborio, J. Suda, T. Kimoto, "1.5 kV Lateral Double RESURF MOSFETs on 4H-SiC (000-1)C Face", Materials Science Forum, Vols. 615-617, pp. 757-760, 2009
Online since
March 2009
Export
Price
$32.00
Share

In order to see related information, you need to Login.

In order to see related information, you need to Login.

Authors: Kazuhiro Fujikawa, Shinsuke Harada, Atsuo Ito, Tsunenobu Kimoto, Hiroyuki Matsunami
1189
Authors: H. Kawano, Tsunenobu Kimoto, Jun Suda, Hiroyuki Matsunami
Abstract:Optimum dose designing for 4H-SiC (0001) two-zone RESURF MOSFETs is investigated by device simulation and fabrication. Simulated results...
809
Authors: Hiroki Niwa, Gan Feng, Jun Suda, Tsunenobu Kimoto
Chapter 6: SiC Devices, Circuits and Systems
Abstract:Breakdown characteristics of 4H-SiC PiN diodes with various JTE structures have been investigated. By combining two-zone JTE and...
973
Authors: Chien Chung Hung, Young Shying Chen, Cheng Tyng Yen, Chwan Ying Lee, Lurng Shehng Lee, Ming Jinn Tsai
Chapter 8: MOS Processing
Abstract:Two-dimensional device simulations of 4H-SiC DMOSFET were performed in this study. Two types of P-Well doping profiles are compared. The...
711
Authors: Andreas Hürner, Luigi Di Benedetto, Tobias Erlbacher, Heinz Mitlehner, Anton J. Bauer, Lothar Frey
Chapter IV: SiC Devices and Circuits
Abstract:In this study, a new robust double-ring junction-termination-extension (DR-JTE) for high-voltage pn-diodes is presented and analyzed using...
656