Fabrication of SiC JFET-Based Monolithic Integrated Circuits
| Periodical | Materials Science Forum (Volumes 645 - 648) |
|---|---|
| Main Theme | Silicon Carbide and Related Materials 2009 |
| Edited by | Anton J. Bauer, Peter Friedrichs, Michael Krieger, Gerhard Pensl, Roland Rupp and Thomas Seyller |
| Pages | 1115-1118 |
| DOI | 10.4028/www.scientific.net/MSF.645-648.1115 |
| Citation | Xiao An Fu et al., 2010, Materials Science Forum, 645-648, 1115 |
| Online since | April, 2010 |
| Authors | Xiao An Fu, Amita Patil, Te Hao Lee, Steven Garverick, Mehran Mehregany |
| Keywords | High Temperature Operation, Integrated Circuit, JFET |
| Price | US$ 28,- |
We report fabrication of lateral, n-channel, depletion-mode, junction-field-effect-transistor (JFET) monolithic analog integrated circuits (ICs) in 6H-SiC. Ti/TaSi2/Pt forms the contact metalization, Ti/Pt the interconnect metal, and the SiO2/Si3N4/SiO2 interlayer dielectric. The threshold voltage and pinch off current indicate that the actual channel doping and thickness is close to the nominal values specified. The wafer yield for good circuits of a single-stage differential amplifier is 54% out of 46 copies.