The optimal control parameters for semiconductor switches at the development state with new materials and structures are often unidentified. By using those sample switches with a gate control set by investigating one switch only, parasitic influences might lead to increased switching losses in half bridges [1, 2]. The focus of this paper is on an effect at turn on by using for example normally on JFET as high and low side switch. At this an increased current peak might occur which leads to higher switching losses. By adjusting the gate voltage losses can be economized.