Paper Title:
Circuit Modeling of Vertical Buried-Grid SiC JFETs
  Abstract

The main problem when the conventional PSpice JFET model is used to simulate a vertical short-channel buried-grid JFET is caused by the constant values of Threshold Voltage (VTO) and Transconductance (BETA). This paper presents a new model for the vertical short-channel buried-grid 1200V JFET, where both VTO and BETA vary with respect to the Drain-Source voltage. Simulation data from Medici have been analyzed in order to extract the analytical equations for VTO and BETA. Also other PSpice parameters are extracted from these data. The proposed circuit model has been simulated in Matlab by optimizing the same algorithm that PSpice uses. A variety of results are shown and discussed in this paper.

  Info
Periodical
Materials Science Forum (Volumes 645-648)
Edited by
Anton J. Bauer, Peter Friedrichs, Michael Krieger, Gerhard Pensl, Roland Rupp and Thomas Seyller
Pages
965-968
DOI
10.4028/www.scientific.net/MSF.645-648.965
Citation
G. Tolstoy, D. Peftitsis, J. K. Lim, M. Bakowski, H. P. Nee, "Circuit Modeling of Vertical Buried-Grid SiC JFETs ", Materials Science Forum, Vols. 645-648, pp. 965-968, 2010
Online since
April 2010
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