The crosstalk is induced between the elements in digital circuits due the increasing switching speeds and the decreasing in technology scaling. The crosstalk is caused by parasitic couplings between adjacent wires that include capacitance and inductance effects. The crosstalk can result in functional failures or timing problems. A test approach for the delay faults caused by crosstalk interferences in digital circuits is presented in this paper, the approach is based on decision diagrams and the selection of delay sensitive path. The static timing analysis is carried out to obtain the delay information about the paths, all aggressor lines are activated in the best possible way. The test vectors are generated by building a decision diagram and searching for the specific paths in the decision diagram. Experimental results show that the test approach proposed in this paper can generate the test vectors for the testable delay faults caused by crosstalk.