3C-SiC MOS Based Devices: From Material Growth to Device Characterization
| Periodical | Materials Science Forum (Volumes 679 - 680) |
|---|---|
| Main Theme | Silicon Carbide and Related Materials 2010 |
| Edited by | Edouard V. Monakhov, Tamás Hornos and Bengt. G. Svensson |
| Pages | 433-436 |
| DOI | 10.4028/www.scientific.net/MSF.679-680.433 |
| Citation | Jean Lorenzzi et al., 2011, Materials Science Forum, 679-680, 433 |
| Online since | March, 2011 |
| Authors | Jean Lorenzzi, Romain Esteve, Nikoletta Jegenyes, Sergey A. Reshanov, Adolf Schöner, Gabriel Ferro |
| Keywords | 3C-SiC, CVD, MOS, VLS Mechanism |
| Price | US$ 28,- |
In this work we report on the growth and preparation of 3C-SiC(111) material for metal-oxide-semiconductor (MOS) application. In order to achieve reasonable material quality to prepare MOS capacitors several and crucial steps are needed: 1) heteroepitaxial growth of high quality 3C-SiC(111) layer by vapour-liquid-solid mechanism on 6H-SiC(0001) substrate, 2) surface polishing, 3) homoepitaxial re-growth by chemical vapour deposition and 4) use of an advanced oxidation process combining plasma enhanced chemical vapour deposition (PECVD) SiO2 and short post-oxidation steps in wet oxygen. Combining all these processes the interface traps density (Dit)can be drastically decreased down to 1.2 1010 eV-1cm-2 at 0.63 eV below the conduction band. To our knowledge, these values are the best ever reported for SiC material in general and 3C-SiC in particular.
