Paper Title:
3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide
  Abstract

3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.

  Info
Periodical
Materials Science Forum (Volumes 679-680)
Edited by
Edouard V. Monakhov, Tamás Hornos and Bengt. G. Svensson
Pages
645-648
DOI
10.4028/www.scientific.net/MSF.679-680.645
Citation
M. Kobayashi, H. Uchida, A. Minami, T. Sakata, R. Esteve, A. Schöner, "3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide", Materials Science Forum, Vols. 679-680, pp. 645-648, 2011
Online since
March 2011
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Price
$32.00
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