Paper Title:
Silicon Carbide Vertical JFET with Self-Aligned Nickel Silicide Contacts
  Abstract

Trenched implanted vertical JFETs (TI-VJFETs) with self-aligned gate and source contacts were fabricated on commercial 4H-SiC epitaxial wafers. Gate regions were formed by aluminium implantation through the same silicon oxide mask which was used for etching mesa-structures. Self-aligned nickel silicide source and gate contacts were formed using a silicon oxide spacer formed on mesa-structure sidewalls by anisotropic thermal oxidation of silicon carbide followed by anisotropic reactive ion etching of oxide. Fabricated normally-on 4H-SiC TI-VJFETs demonstrated low gate leakage currents and blocking voltages exceeding 200 V.

  Info
Periodical
Materials Science Forum (Volumes 679-680)
Edited by
Edouard V. Monakhov, Tamás Hornos and Bengt. G. Svensson
Pages
670-673
DOI
10.4028/www.scientific.net/MSF.679-680.670
Citation
K. Vassilevski, I. P. Nikitina, A. B. Horsfall, N. G. Wright, A. J. Smith, C. M. Johnson, "Silicon Carbide Vertical JFET with Self-Aligned Nickel Silicide Contacts", Materials Science Forum, Vols. 679-680, pp. 670-673, 2011
Online since
March 2011
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Price
$32.00
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