Advanced Surface Cleaning Strategy for 65nm CMOS Device Performance Enhancement |
| Journal |
Solid State Phenomena (Volumes 103 - 104) |
| Volume |
Ultra Clean Processing of Silicon Surfaces VII |
| Edited by |
Paul Mertens, Marc Meuris and Marc Heyns |
| Pages |
37-40 |
| DOI |
10.4028/www.scientific.net/SSP.103-104.37 |
| Online since |
April, 2005 |
| Authors |
F. Arnaud,
H. Bernard,
Alessio Beverina,
R. El-Farhane,
B. Duriez,
Kathy Barla,
Didier Lévy
|
| Keywords |
CMOS Device Performance, Dopant Consumption, Low Temperature Cleaning |
| Abstract |
This paper investigates low temperature cleaning steps solutions (T°<30°) developed to enhance the 65nm transistor performance. A complete cleaning recipes optimization is realized in term of silicon consumption and defectiveness for pre-furnace clean (RCA or HFRCA), post gate etch clean PGEC (HF-SPM-SC1) and post ash clean PAC (SPM–SC1) operations. The silicon recess and the dopants consumption are reduced by using low temperature SC1 steps. Transistor drivability is improved by 8% and 7% for NMOS and PMOS respectively. |
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