Paper Title:
Advanced Surface Cleaning Strategy for 65nm CMOS Device Performance Enhancement
  Abstract

This paper investigates low temperature cleaning steps solutions (T°<30°) developed to enhance the 65nm transistor performance. A complete cleaning recipes optimization is realized in term of silicon consumption and defectiveness for pre-furnace clean (RCA or HFRCA), post gate etch clean PGEC (HF-SPM-SC1) and post ash clean PAC (SPM–SC1) operations. The silicon recess and the dopants consumption are reduced by using low temperature SC1 steps. Transistor drivability is improved by 8% and 7% for NMOS and PMOS respectively.

  Info
Periodical
Solid State Phenomena (Volumes 103-104)
Edited by
Paul Mertens, Marc Meuris and Marc Heyns
Pages
37-40
DOI
10.4028/www.scientific.net/SSP.103-104.37
Citation
F. Arnaud, H. Bernard, A. Beverina, R. El-Farhane, B. Duriez, K. Barla, D. Lévy, "Advanced Surface Cleaning Strategy for 65nm CMOS Device Performance Enhancement", Solid State Phenomena, Vols. 103-104, pp. 37-40, 2005
Online since
April 2005
Export
Price
$32.00
Share

In order to see related information, you need to Login.

In order to see related information, you need to Login.

Authors: Chun Jen Weng
Abstract:As the nanotechnology gate is scaling down, the fabrication technology of gate spacer for CMOS transistor becomes more critical in...
91
Authors: Li Cheng, Jia Jian Xi, Ning Li, Ning Yang
Chapter 2: Material Science and Technology
Abstract:In order to obtain high-speed and large-drive-current during operation, this paper proposed two structure-advanced BiCMOS analog switches. On...
1245
Authors: K. Senthil Kumar, Saptarsi Ghosh, Anup Sarkar, S. Bhattacharya, Subir Kumar Sarkar
Chapter 23: Computer-Aided Design, Manufacturing, and Engineering
Abstract:With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in...
5150
Authors: Guang Yaw Hwang, J.H. Liao, S.F. Tzou, Mark Lin, Autumn Yeh, David Lou, Eason Chen, Weien Huang, Gowri Kamarthy, Kai Dong Xu, Amulya Athayde
Chapter 1: FEOL Surface Chemistry, Etching and Passivation
Abstract:Beginning at the 45nm node, the semiconductor industry is moving to high-k gate dielectrics and metal gate electrodes for CMOS logic devices...
57
Authors: R.A.R. Young, David Clark, Jennifer D. Cormack, A.E. Murphy, Dave A. Smith, Robin. F. Thompson, Ewan P. Ramsay, S. Finney
Chapter 10: Device and Application
Abstract:Silicon Carbide devices are capable of operating as a semiconductor at high temperatures and this capability is being exploited today in...
1065