Paper Title:
Effects of Electroplating Parameters on the Defects of Copper via for 3D SiP
  Abstract

Electroplating of copper in via filling is very important in 3D SiP (System in Packaging). Defect free via filling can be obtained through additive in the electrolyte and current type control. Via in Si wafer were formed by RIE method with 170 &m depth and 50 &m in diameter. Seed layers were deposited by ionized metal plasma (IMP) sputtering; Ta for diffusion barrier, Cu for conductive layer. Via was filled with copper by electroplating method. Different types of additives were used in via filling; PEG, SPS, Cl- and JGB. Defects in via were controlled and eliminated by precise monitoring of additive concentration and input current. The optimum condition of electroplating was determined by getting cross-sectional images of filled vias and by determining the degree of via filling.

  Info
Periodical
Solid State Phenomena (Volumes 124-126)
Edited by
Byung Tae Ahn, Hyeongtag Jeon, Bo Young Hur, Kibae Kim and Jong Wan Park
Pages
49-52
DOI
10.4028/www.scientific.net/SSP.124-126.49
Citation
B. H. Cho, W. J. Lee, J. H. Lee, "Effects of Electroplating Parameters on the Defects of Copper via for 3D SiP", Solid State Phenomena, Vols. 124-126, pp. 49-52, 2007
Online since
June 2007
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Price
$32.00
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