Electrical Uniformity of Direct Silicon Bonded Wafer Interfaces
| Periodical | Solid State Phenomena (Volumes 131 - 133) |
|---|---|
| Main Theme | Gettering and Defect Engineering in Semiconductor Technology XII |
| Edited by | A. Cavallini, H. Richter, M. Kittler and S. Pizzini |
| Pages | 321-326 |
| DOI | 10.4028/www.scientific.net/SSP.131-133.321 |
| Citation | Magnus C. Wagener et al., 2007, Solid State Phenomena, 131-133, 321 |
| Online since | October, 2007 |
| Authors | Magnus C. Wagener, R.H. Zhang, W. Zhao, M. Seacrist, M. Ries, George A. Rozgonyi |
| Keywords | Direct Silicon Bond, Grain Boundary, Hybrid Orientation, Interface States (or Traps) |
| Price | US$ 28,- |
This paper describes a series of electrical measurements and sample modifications that enabled the electrical properties of hybrid-orientation direct silicon bonded wafer interfaces to be determined. It is shown that the carrier transport across this near-surface (110)Si/(100)Si boundary is dictated by the defects present at the bond interface. These interface states are believed to pin the Fermi-level, producing a conduction barrier with a thermal activation energy Ea = 0.56eV. The defect band has been identified by deep-level transient spectroscopy and associated with the defect states typically observed in plastically deformed silicon. The carrier transport behavior across the bonding interface, as well as the observed interface trap levels are therefore attributed to the dislocation network present at the bonding interface. The spatial uniformity of the interface properties have been evaluated by TEM, electron-beam induced current microscopy, photoconductive decay and conduction measurements.
