Paper Title:
Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA
  Abstract

Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) of Virtex family. Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration.

  Info
Periodical
Solid State Phenomena (Volume 144)
Edited by
Inga Skiedraite and Jolanta Baskutiene
Pages
214-219
DOI
10.4028/www.scientific.net/SSP.144.214
Citation
V. Abraitis, Ž. Tamoševičius, "Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA", Solid State Phenomena, Vol. 144, pp. 214-219, 2009
Online since
September 2008
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