In the semiconductor industry, the edge exclusion of processed wafers is decreasing to accommodate more integrated circuits. With this trend, there is a higher risk of detrimental contamination at the wafer edge and bevel making the monitoring for metallic contamination in these areas critical. Cross contamination from the edge and bevel can occur at many processing steps. For example, metals can spread from the wafer edge, bevel and backside to the wafer’s surface in a wet cleans process. In immersion lithography, the water drop that is scanned across the wafer could transport contamination from the edge and deposit it across the wafer surface. Contamination on wafer edge and bevel can have many origins; handling systems in every process tool, reaction products in etching, and residuals of new materials in high-k for CVD and PVD, for example. To know what metallic contamination is present, and to investigate the causes are essential for wafer edge control.