Paper Title:
Low Temperature Pre-Epi Treatment: Critical Parameters to Control Interface Contamination
  Abstract

Several device concepts have been further evaluated after the successful implementation of epitaxial Si, SiGe and/or Si:C layers. Most of the next device generations will put limitations on the thermal budget of the deposition processes without making concessions on the epitaxial layer quality. In this work we address the impact of ex-situ wet chemical cleans and in-situ pre-epi bake steps, which are required to obtain oxide free Si surfaces for epitaxial growth. The combination of defect measurements, Secondary Ion Mass Spectroscopy, photoluminescence, lifetime measurements, and electrical diode characterization gives a very complete overview of the performance of low-temperature pre-epi cleaning methods. Contamination at the epi/substrate interface cannot be avoided if the pre-epi bake temperature is too low. This interface contamination is traceable by the photoluminescence and lifetime measurements. It may affect device characteristics by enhanced leakage currents and eventually by yield issues due to SiGe layer relaxation or other defect generation. A comparison of state of the art 200 mm and 300 mm process equipment indicates that for the same thermal budgets the lowest contamination levels are obtained for the 300 mm equipments.

  Info
Periodical
Solid State Phenomena (Volumes 145-146)
Edited by
Paul Mertens, Marc Meuris and Marc Heyns
Pages
177-180
DOI
10.4028/www.scientific.net/SSP.145-146.177
Citation
R. Loo, A. Hikavyy, F. E. Leys, M. Wada, K. Sano, B. De Vos, A. Pacco, M. Bargallo Gonzalez, E. Simoen, P. Verheyen, W. Vanherle, M. Caymax, "Low Temperature Pre-Epi Treatment: Critical Parameters to Control Interface Contamination", Solid State Phenomena, Vols. 145-146, pp. 177-180, 2009
Online since
January 2009
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Price
$32.00
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