Post Extension Ion Implant Photo Resist Strip for 32 nm Technology and beyond
| Periodical | Solid State Phenomena (Volumes 145 - 146) |
|---|---|
| Main Theme | Ultra Clean Processing of Semiconductor Surfaces IX |
| Edited by | Paul Mertens, Marc Meuris and Marc Heyns |
| Pages | 253-256 |
| DOI | 10.4028/www.scientific.net/SSP.145-146.253 |
| Citation | G. Mannaert et al., 2009, Solid State Phenomena, 145-146, 253 |
| Online since | January, 2009 |
| Authors | G. Mannaert, L. Witters, Denis Shamiryan, Werner Boullart, K. Han, S. Luo, A. Falepin, R. Sonnemans, Ivan L. Berry, Carlo Waldfried |
| Keywords | Dopant Loss, Fin, Photoresist Strip |
| Price | US$ 28,- |
The most advanced technology nodes require ultra shallow extension implants (low energy) which are very vulnerable to ash related substrate oxidation, silicon and dopant loss, which can result in a dramatic increase of the source/drain resistance and shifted transistor threshold voltages. A robust post extension ion implant ash process is required in order to meet cleanliness, near zero Si loss and dopant loss specifications. This paper discusses a performance comparison between fluorine-free, reducing and oxidizing, ash chemistries and “as implanted – no strip” process conditions, for both state-of-the-art nMOS and pMOS implanted fin resistors. Fluorine-free processes were chosen since earlier experiments with fluorine containing plasma strips exhibited almost a 10x increase in sheet resistance in the worse case.