High Resolution High Power Low Frequency Digital-to-Analog Converter

The architectural scheme of the designed Sigma-Delta DAC on the FPGA is considered. The place of the interpolator in Sigma-Delta DACs is briefly discussed. The summarized structure of the most common interpolators is presented. More applicable structures of interpolators were suggested and analyzed, providing the comparison with [1]. Having changed the structure of the incomplete interpolator and having optimized the stages, it was possible to improve the characteristic of amplitude frequency response with a smaller number of non-zero coefficients and much lower FPGA resources. The paper provides simulated results of the interpolator filter transmission characteristics as well as Sigma-Delta modulator quantization noise parameters. It is demonstrated that simulation of the complete converter system (interpolator + modulator + output filter) allows to identify places of the interpolator, where hardware resources could be saved, thereby reducing the chip area occupied by the converter, which is not always obvious when analyzing nodes separately. Therefore another version of the interpolator was proposed for the system ensuring larger suppression of the additional frequency band in the whole system compared with the previous interpolator. Simulated results related to occupied chip resources are also confirmed by the experiment, which was implemented in Xilinx Spartan FPGA.