Deposition Wet-Etching Deposition (DWD) Method for Polysilicon Gate Fill-In at Flash Memory

Chiang, Chun Ling; Cheng, C.M.; Liao, J.H.; Lin, H.J.; Yeh, C.C.; Hsieh, J.Y.; Yang, L.W.; Yang, T.H.; Chen, K.C.; Lu, Chih Yuan

Paper Titles

Achieving Ultra-Shallow Junctions in Future CMOS Devices by a Wet Processing Technique, p.33
Effect of Wet Cleanings on GST Surface: XPS Characterization, p.37
Study of the Etching Mechanism of Heavily Doped Si in HF, p.41
Study on Al₂O₃ Film in Anhydrous HF Vapor, p.45
Deposition Wet-Etching Deposition (DWD) Method for Polysilicon Gate Fill-In at Flash Memory, p.49
Poly-Silicon Wet Removal for Replacement Gate Integration Scheme: Impact of Process Parameters on the Removal Rate, p.53
A Hybrid Dry-Wet Approach for Removal of a Dummy Polysilicon Gate in a Replacement Metal Gate Scheme, p.57
Static Charge Induced Damage during Lightly Doped Drain (LDD) by Single Wafer Cleaning Process, p.63
Surface Charging Induced Gate Oxide Degradation, p.67

Home > Solid State Phenomena > Ultra Clean Processing of Semiconductor Surfaces X > Deposition Wet-Etching Deposition (DWD) Method for...

Paper Title:

Deposition Wet-Etching Deposition (DWD) Method for Polysilicon Gate Fill-In at Flash Memory

Periodical	Solid State Phenomena (Volume 187)
Main Theme	Ultra Clean Processing of Semiconductor Surfaces X
Edited by	Paul Mertens, Marc Meuris and Marc Heyns
Pages	49-52
DOI	10.4028/www.scientific.net/SSP.187.49
Citation	Chun Ling Chiang et al., 2012, Solid State Phenomena, 187, 49
Online since	April, 2012
Authors	Chun Ling Chiang, C.M. Cheng, J.H. Liao, H.J. Lin, C.C. Yeh, J.Y. Hsieh, L.W. Yang, T.H. Yang, K.C. Chen, Chih Yuan Lu
Keywords	APM, Polysilicon, Wet-Etching Deposition (DWD)
Price	US$ 28,-

View full size

Abstract

The present study aims at polysilicon material fill-in at re-entrant profile at flash memory product. The void was observed after polysilicon fill-in. In order to prevent the void formation, the multi-step process of deposition wet-etching deposition (DWD) method was evaluated. The DWD method is found to play beneficial roles in achieving void-free in the floating gate. The high concentration of NH₄OH in APM was choosing for wet etching solution. Scanned electron microscopy (SEM) and transmission electron microscopy (TEM) were employed to measure the polysilicon thickness and cross-section profile of device.