Papers by Author: Aivars J. Lelis

Abstract: We utilize electrically detected magnetic resonance (EDMR) via spin dependent recombination (SDR) to provide a definitive identification of an interface/near interface defect present in a wide variety of 4H SiC/SiO2 metal oxide semiconducting field effect transistors (MOSFETs).

Abstract: We present transition layer electron mobility versus field curves for several 4H-SiC/SiO2 structures, simulated by a newly developed Monte Carlo simulator that uses density of states calculated by density functional theory (DFT). Our calculations show that among all structures, abrupt SiC/SiO2 has the highest transition layer mobility.

Abstract: We have investigated the thermal behavior of our recently developed 1200 V, 200 A 4H-SiC power DMOSFETs operating from 20°C up to 300°C. Compared to the first generation SiC DMOSFET that was commercially released early this year, this 4H-SiC power DMOSFET shows a ~ 50% reduction in the total specific on-resistance at room temperature. Temperature dependence of the key parameters of this MOSFET, such as on-resistance, threshold voltage, and the MOS channel mobility, are reported in this paper. The MOSFET showed normally-off characteristics throughout the entire experimental temperature range. Different temperature dependence of the total on-resistance in different temperature regimes has been observed.

Abstract: A two-way tunneling model describing simultaneous oxide trap charging and discharging in SiC MOSFETs is presented, along with a comparison with experimental results. This model can successfully account for the variation in threshold-voltage instability observed as a function of bias-stress time, bias-stress magnitude, and measurement time.

Abstract: We compare the effect of hydrogen, nitrogen, and phosphorous passivation on total near interface trap density and mobility of 4H(0001)-SiC/SiO2 structure. The results show that nitrogen and phosphorous passivation decrease total near interface trap density by pushing the energy levels of interface traps away from the conduction band. The density of states (DOS), including interface states (Dit), are calculated for several 4H(0001)-SiC/SiO2 structures using density functional theory (DFT).

Abstract: Since power devices such as DMOSFETs will operate at high temperature where mobile ion effects are enhanced, identifying their presence is a key reliability issue for power electronics applications. We have detected the presence of mobile ion contamination in some SiC MOS device sample sets and correlated those results with observed high temperature bias instability. The differing behaviors of these devices to bias stressing as a function of temperature suggests that in some cases mobile ion drift may be counteracting the typical charge trapping effect. Triangular voltage sweep (TVS) data indicates the presence of roughly 1-4x10¹² cm^-2 mobile ions in samples where the bias instability significantly decreased with higher temperature, while samples with a nearly flat or positive-trending response showed overall lower ion contaminations of roughly 6-9x10¹¹ cm^-2. These results, although preliminary, support the theory that mobile ion contamination is the cause of negative bias instability at elevated temperatures in SiC MOS.

Abstract: Electron-hole recombination-induced stacking faults have been shown to degrade the electrical characteristics of SiC power pin and MPS diodes and DMOSFETs with thick drift epitaxial layers. In this paper, we investigate the effects of bipolar injection induced stacking faults on the electrical characteristics of p+ ion-implanted high-voltage vertical-channel JFETs with 100-μm drift epilayers. The JFETs were stressed at a fixed gate-drain bipolar current density of 100 A/cm² for five hours, which led to degradation of the forward gate-drain p-n junction and on-state conduction. The degradation was fully reversed by annealing at 350 °C for 96 hours. Forward and reverse gate-source, transfer, reverse gate-drain, and blocking voltage JFET characteristics exhibit no degradation with bipolar stress. Non-degraded characteristics remain unaffected by annealing events. Consequently, should minority carrier injection occur in JFETs operating at elevated temperatures no stacking fault induced degradations are expected. This eliminates the need for specialty substrates with suppressed densities of basal plane dislocations in the fabrication of high-voltage SiC JFETs for high temperature applications.

Abstract: We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.

Abstract: Threshold voltage (VT) instability remains an important issue for the performance, reliability, and qualification of SiC power MOSFET devices. The direct application of existing reliability test standards to SiC power MOSFETs can in some cases result in an inconsistent pass/fail response for a given device. To ensure SiC MOSFET device reliability, some modifications to existing test methods may be necessary..

Abstract: Normally-ON 9.1 kV (at 0.1 mA/cm2), 1.52 x 10-3 cm2 active-area vertical-channel SiC JFETs (VJFETs), were fabricated at a 52% yield with no epitaxial regrowth and a three-step junction-termination-extension edge termination, which is connected to the gate bus through an ion-implanted sloped sidewall. The VJFETs exhibit low gate-to-source leakage currents of less than 1 nA up to VGS = -60 V, and sharp onsets of breakdown occurring at VGS ~ -80 V. The gate-to-source and gate-to-drain diodes turn on at 2.75 V, with the latter diode exhibiting higher resistance due to the thick epitaxial drift layer. To realize unipolar operation with low on-state resistance, the VJFET is designed very normally-ON which minimizes the channel resistance contribution. Consequently, threshold voltages are in the -3 V to -4.5 V range and transconductance is relatively low at < 0.36 mS. At a gate bias of 0 V, the VJFETs output a drain current of 73 mA with a forward drain voltage drop of 5 V (240 W/cm2), a specific on-state resistance of 104 mΩ-cm2, and a current gain of ID/IG = 6.4 x 109. Thus, these VJFETs are capable of efficient power switching, i.e., high current-gain voltage-controlled operation at a low unipolar resistance.