Papers by Author: Anant K. Agarwal

Abstract: MOSFETs and capacitors have been fabricated to investigate the atomic layer depositon (ALD) of SiO₂ onto SiC compared to thermal oxidation of SiC. Devices were fabricated on 4H-SiC with the following oxidation treatments: thermal oxidation at 1175°C, thermal oxidation at 1175°C followed by a nitric oxide (NO) anneal at 1175°C, and ALD of SiC at 150°C followed by an NO post oxidation anneal (POA) at 1175°C. ALD of the SiO₂ was performed using 3-aminopropyltriethoxysiliane (3-APTES), ozone and water. Capacitors fabricated with NO annealed ALD oxide and thermal oxide with NO POA exhibited similar CV behavior and yielded similar Dit of 1e11 at 0.5 eV from the conduction band. MOSFETs fabricated with NO PDA ALD oxide exhibited peak field effect mobilities ranging from 32 – 40.5 cm2/Vs compared to 30 –34.5 cm2/Vs for the MOSFETs with NO annealed thermal oxide. The higher mobilities exhibited by the ALD gate oxides were linked through SIMS to higher nitrogen concentrations at the SiO₂/SiC interface.

Abstract: In this paper, we report our recently developed 1 cm², 15 kV SiC p-GTO with an extremely low differential on-resistance (_RON,diff) of 4.08 mΩ•cm² at a high injection-current density (J_AK) of 600 ~ 710 A/cm². The 15 kV SiC p-GTO was built on a 120 μm, 2×10¹⁴/cm³ doped p-type SiC drift layer with a device active area of 0.521 cm². Forward conduction of the 15 kV SiC p-GTO was characterized at 20°C and 200°C. Over this temperature range, the R_ON,diff at J_AK of 600 ~ 710 A/cm² decreased from 4.08 mΩ•cm² at 20°C to 3.45 mΩ•cm² at J_AK of 600 ~ 680 A/cm² at 200°C. The gate to cathode blocking voltage (V_GK) was measured using a customized high-voltage test set-up. The leakage current at a V_GK of 15 kV were measured 0.25 µA and 0.41 µA at 20°C and 200°C respectively.

Abstract: We have investigated the thermal behavior of our recently developed 1200 V, 200 A 4H-SiC power DMOSFETs operating from 20°C up to 300°C. Compared to the first generation SiC DMOSFET that was commercially released early this year, this 4H-SiC power DMOSFET shows a ~ 50% reduction in the total specific on-resistance at room temperature. Temperature dependence of the key parameters of this MOSFET, such as on-resistance, threshold voltage, and the MOS channel mobility, are reported in this paper. The MOSFET showed normally-off characteristics throughout the entire experimental temperature range. Different temperature dependence of the total on-resistance in different temperature regimes has been observed.

Abstract: The Army Research Laboratory has collaborated with Cree, Inc. and Silicon Power Corp. to develop 9 kV-blocking, 1.0 cm² Super-GTOs. In this study, several 1.0 cm² GTOs were individually switched up to 6.0 kA in a low-inductance, high dI/dt (2.1 kA/µs) circuit to evaluate turn-on delay and optimize the gate control. Turn-on delay was evaluated relative to gate drive current, and the delay was reduced by 1.1 µs when gate amplitude was increased from 1 A to 8 A. Increasing gate current delivered to each GTO also successfully reduced variation in turn-on delay from device to device by at least 50%, and mitigated mismatch in turn-on between pairs of GTOs switched in parallel. As silicon carbide material processing and device development continue to evolve, the ultimate solution will be to reduce remaining material defects and to control minority carrier diffusion length through more uniform doping across the wafer. These steps will enable modules of parallel GTOs to perform at maximum capability.

Abstract: Hall measurements on NO annealed 4H-SiC MOS gated Hall bars are reported in the temperature range 77 K- 423 K. The results indicate higher carrier concentration and lower trapping at increased temperatures, with a clear strong inversion regime at all temperatures. In stark contrast to Si, the Hall mobility increases with temperature for 77 K-373K, above which the mobility decreases slightly. The maximum experimental mobility was found to be ~50 cm² V^-1 s^-1 which is only about 10% of the 4H-SiC bulk mobility indicating that while NO annealing drastically improves trapping, it does not improve the mobility significantly. Supporting modeling results strongly suggest the presence of a disordered SiC channel region.

Abstract: The effects of Shockley stacking faults (SSFs) that originate from half loop arrays (HLAs) on the forward voltage and reverse leakage were measured in 10 kV 4H-SiC PiN diodes. The presence of HLAs and basal plane dislocations in each diode in a wafer was determined by ultraviolet photoluminescence imaging of the wafer before device fabrication. The SSFs were expanded by electrical stressing under forward bias of 30 A/cm², and contracted by annealing at 550 °C. The electrical stress increased both the forward voltage and reverse leakage. Annealing returned the forward voltage and reverse leakage to nearly their original behavior. The details of SSF expansion and contraction from a HLA and the effects on the electrical behavior of the PiN diodes are discussed.

Abstract: We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 6.7 mm x 6.7 mm 4H-SiC N-IGBT with an active area of 0.16 cm2 showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. A 4H-SiC P-IGBT exhibited a record high blocking voltage of 15 kV, while showing a differential specific on-resistance of 24 mΩ-cm2. A comparison between P- and N- IGBTs in 4H-SiC is provided in this paper.

Abstract: We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.

Abstract: 4H-SiC MOSFETs with an epitaxial channel and NO postoxidation annealing have Si-like dependencies of noise on gate voltage. Such dependencies indicate that the density of the negatively charged oxide traps responsible for 1/f noise, N_tv, does not depend on the position of the Fermi level. The N_tv was found to be ~ 2×10¹⁹ cm^-3eV^-1. This value is considerably smaller than previously measured for transistors with ion implanted channels.

Abstract: In this paper, for the first time, we report 12 kV, 1 cm² SiC GTOs demonstrated with a novel negative bevel termination, which improves the breakdown voltage by >3.5 kV compared to the conventional multiple-zone Junction Termination Extension (JTE). The significant improvement in the blocking voltage was attributed to the elimination of the electrical field crowding in the periphery of the mesa with conventional JTE termination. This new termination has been used in both electrically and optically triggered SiC GTOs. An ultrafast turn-on speed of 70 ns has been measured on 12 kV, 1 cm² SiC light triggered GTOs.