Papers by Author: Anton J. Bauer

Abstract: Contamination control is essential in semiconductor manufacturing to ensure high yield and product quality. Latest power electronic devices are manufactured in fully automated 300 mm production lines, which utilize closed wafer containers called Front Opening Unified Pods (FOUPs). It has been observed, that FOUPs capture airborne molecular contaminants (AMC) outgassing from processed wafers or being transferred from the equipment minienvironment. These AMC might be released afterwards and can lead to defects causing yield and/or reliability issues of the power devices. Specific FOUP cleaning and exchange rules are already being utilized in the fab. But so far, these rules are not validated or adapted by actual concentration values in the FOUPs. In this paper, contamination levels in FOUPs are investigated to identify the sources of different AMC. The contamination data is analysed together with FOUP logistics data in order to establish an optimized FOUP management strategy. In the first part, in-line carrier contamination control is explained and a general overview of the AMC detected is given. In the second part, the data-driven FOUP-monitoring is described using the example of the root cause analysis of hydrofluoric acid (HF) contamination.

Abstract: The compensation of charge carriers is an important aspect to be considered in Aluminum doped areas in 4H-SiC. In this paper, a straightforward method has been found to implement compensation effects into a basic device simulation model and to improve the conformance of electrical measurement and simulation results. By implementing the compensation factors, which depend on Aluminum doping concentration, device simulation in combination with basic device cell structure can be used to create electrical characteristics that are in accordance with measured characteristics. This is a simple alternative for complex process simulation, taking into account physical effects like defects in the crystal structure. The method was used for simulation of lateral MOSFETS transfer characteristic as well as VDMOS blocking characteristic. Found compensation values were 80 % in the 1.5 ∙ 10¹⁷ cm^-3 Al-doped channel region and 23% in the deep, 7.5 ∙ 10¹⁷ cm^-3 Al-doped, shielding region.

Abstract: In this work, the impact of channel implantations (IMP) on the electrical characteristics of SiC n-and p-MOSFETs and analog SiC-CMOS operational amplifiers (OpAmp) is investigated. For this purpose, MOSFETs and Miller OpAmps with and without IMP were fabricated and electrically characterized from room temperature up to 350°C. For devices with IMP the absolute values of the threshold voltages of n-and p-MOSFETs were reduced by 1.5 V and the mobility of the n-MOSFET was increased from 13 to 23 cm2/Vs whereas the mobility of the p-MOSFET remained constant at 6 cm2/Vs. For the resulting OpAmp with IMP, the common-mode input voltage range as well as the open loop gain was increased by 1.5 V and 4 dB compared to non-implanted devices. This improvement was observed across the entire analyzed temperature range from room temperature up to 350°C.

Abstract: In this study, UV Photoluminescence (UVPL) and Differential Interference Contrast (DIC) mapping was applied for process control of a 1.2 kV 4H-SiC VDMOS fabrication process at different process stages in order to investigate the influence of shallow pits on the electrical behavior of the devices. In particular, it could be shown that UVPL and DIC mapping allows the correlation of shallow pits and the occurrence of darker regions in the UVPL images and distinguishing differently implanted regions at distinct process stages. By comparing the darker regions of the UVPL scan with the electrical blocking characteristics of the associated devices a direct correlation between the occurrence of shallow pits and the reduction of the blocking capability of the devices could be observed.

Abstract: In this work, pulsed-laser-based tempering was applied for post-implant annealing of n-type N-doped 4H-SiC in order to electrically activate the dopants and to rebuild the crystal structure. The annealing was performed by a frequency-tripled Nd:YVO₄ laser with a pulse duration of 60 ns. To evaluate the effects of post-implant annealing, JBS diodes were electrically characterized. The results were compared with implanted, not post-annealed JBS diodes. The electrical measurements showed a significant on-state voltage drop of 40 mV at 6 A for post-implant laser annealed diodes compared to not post-implant annealed diodes.

Abstract: In this work, the influence of pre-deposition interfacial oxidation or post-deposition interface nitridation on the performance of 4H-SiC MOS capacitors was investigated. The gate oxide was deposited by LPCVD using TEOS as a precursor. Interface breakdown strength was derived from leakage current and Time-Zero Dielectric Breakdown characteristics whereas interface quality was assessed by the determination of interface state density from the comparison of quasi-static and high frequency capacitance-voltage characteristics using high-low method. In the experimental results, it is demonstrated that the gate oxide deposited by LPCVD using TEOS which is post-deposition annealed in nitric oxide ambient is advantageous for trench-gate MOSFET due to its effectiveness for improving the interface quality and oxide reliability, whereas pre-deposition interfacial oxidation is deleterious to interface state density and breakdown strength.

Abstract: In this study, Al and N implantation effect on surface properties of 4H-SiC epitaxial layers were investigated before annealing process. AFM results indicated that all implanted samples indicated relatively low RMS roughness values. From UPS and XPS analysis, work function and Si-C binding energy of implanted samples were increased compared to the reference 4H-SiC sample. Those variations may be caused by lattice disorder and amorphization. In addition, TEM image showed damaged area in 4H-SiC epitaxial layer.

Abstract: Aluminum implanted 4H-SiC often shows an unexpected increase of the free hole density at elevated temperatures in Hall Effect measurements. Here we show that this phenomenon cannot solely be traced down to the Hall scattering factor and the presence of excited acceptor states. It is necessary to assume an additional defect center in the lower half of the band gap with ionization energies higher than that of aluminum to explain this behavior. Therefore, we investigated ion-implanted square van-der-Pauw samples with Hall Effect and complementary SIMS measurements. An analysis of the data using the neutrality equation reveals compensation ratios of 20 % to 90 %, depending on the aluminum concentration and the concentration of the deep defect center of up to 50 % of the doping.

Abstract: A comparison between self-aligned process (using lift-off) and Ni-SALICIDE used in fabrication of ohmic contacts for SiC Power MOSFET is done. Both processes are demonstrated for 3.3 kV SiC VDMOS transistors fabricated on 100 mm substrates. It is shown that the Ni-SALICIDE process with first silicidation at 500 °C does not degrade the electrical properties of silicon dioxide; particularly, a degradation of the interlayer dielectric between source and gate is not evident. Additionally, this first silicidation is found to have a positive impact on the specific resistance of contacts formed on p-type SiC using NiAl2.6% as an ohmic metal.

Abstract: During ion implantation into monocrystalline semiconductors, some of the implanted atoms will be deflected to crystal directions along which they may penetrate deeply into the crystal. We investigate such channeling effects for Al and N implantation into 4H-SiC by Monte Carlo simulations. The focus of the work is on the effects of channeling on doping profiles, the relevance for the net doping of typical power electronic devices, and the influence of scattering oxides.