Papers by Author: Birgit Kallinger

Abstract: Precise control of optical transitions of color centers like silicon vacancies (V_Si) in 4H-SiC is essential for their functionalization. An applied electric field (E || c) of a pin-diode can be used to tune the optical properties of V_Si centers via the Stark effect, while the associated space charge region under bias suppresses spectral diffusion. Unlike commonly used 4H-SiC c-plane wafers, a-plane wafers allow a scalable fabrication of lateral pin-diodes and resonant laser excitation of the V_Si perpendicular to the wafer surface (a ⊥ c). In this work non-circular lateral pin-diodes oriented perpendicular to the wafer flat were produced in a scalable, CMOS-compatible process. Electrical characterization revealed that 97% of the devices on an a-plane wafer with n-type epitaxial layer were functional, exhibiting breakdown voltages exceeding 200 V and reverse currents below 100 pA/µm, enabling low current noise during optical measurements. The diodes remained operational at cryogenic temperatures after frozen-out charge carriers were re-ionized by the applied electric field. Electron irradiation followed by thermal annealing at 600 °C was used to generate V2 silicon vacancies in the intrinsic region without significantly altering the electrical characteristics. Optically detected magnetic resonance (ODMR) measurements on selected single emitters confirmed the presence of V2 centers by detecting a contrast at 70 MHz, while cryogenic photoluminescence (PL) spectra revealed a zero-phonon line (ZPL) peak at 916 nm.

Abstract: Silicon vacancies (V_Si) are relevant for quantum technologies, including sensing, computing, and communication. For the realization of quantum photonic integrated circuits (QPICs) and, therefore, co-integration of optical and electrical devices with resonant excitation through the wafer surface, a-plane 4H-SiC wafers are required. Transferring established complementary metal-oxide-semiconductor (CMOS)-compatible processes from c-plane to a-plane wafers is, therefore, a crucial step. In this work, key fabrication steps, namely ion implantation, thermal oxidation, and ohmic contact formation, were investigated for a-plane 4H-SiC substrates. To demonstrate successful process transfer, p-channel MOS field-effect transistors were fabricated and electrically characterized, showing comparable I_on/I_off ratios and mobilities to their c-plane counterparts, but with a threshold voltage shift from −7.1 V to −12.0 V on the a-plane. Additionally, tunneling diodes were realized as broadband light emitters, with a significant portion of the emission spectrum falling within the range of off-resonant excitation of V_Si centers. The devices maintained light emission functionality down to cryogenic temperatures.

Abstract: An area of increasing interest for SiC device processing is the processing and qualification of silicon oxides. In this article a contactless corona CV (CnCV) measurement procedure is evaluated as a way to gain more knowledge about the different processes related to oxides. A 21-point measurement pattern is used to gain information about uniformity of oxide properties. Two different types of oxides have been considered, low pressure chemical vapor deposited (CVD) oxides using tetraethylorthosilicate (TEOS) and thermally grown oxides. The two different groups have received different combinations of pre- and post-processing steps prior to measurements. As expected, low pressure CVD (LPCVD) and thermally grown SiO₂ without any post oxidation annealing (POA) showed significantly different electrical characteristics compared to the wafers that did get a POA. This difference could clearly be distinguished by CnCV, meaning that individual process steps can be analyzed without the fabrication of any test structures on the wafers. As the individual process steps can be analyzed, the uniformity of the individual steps can be accessed. Using a 21-point pattern it was possible to show that there is a non-uniformity in the LPCVD process used prior to the POA. This makes the CnCV technique suitable for in-line characterization and process monitoring.

Abstract: This paper compares ethene and methane precursors for homoepitaxial 4H-SiC growth in planetary reactors with regards to their impact on growth rate and defectivity of the epilayers. Therefore, a comprehensive experimental study has been performed in AIXTRON G10-SiC and G5WW C planetary reactors using a standard process based on ethene and trichlorosilane precursors with conventional 150 mm n-type 4H-SiC substrates from 3 different international suppliers. Methane substituted ethene as precursor in many experiments. It was found that methane precursor can compete with ethene in terms of growth rate, epilayer thickness, and defectivity of the epilayers. By using isotopically enriched methane, Si¹²C epilayers with a ¹²C concentration of 99.96 % have been grown which can be used for SiC-based quantum technology.

Abstract: The yield of power electronic devices is influenced by many factors including crystal defects like stacking faults (SFs). There are different types of stacking faults but their influence on the finished device and its performance and the behavior of SF during processing is not fully understood yet. With our contribution, we shed light on the issue, showing four different optically characterized subtypes of SFs with different electrical behavior that can already be found after implantation and wafer annealing in photoluminescence (UVPL) imaging. This enables a distinction between different SF classes without the need for a finally processed device and the corresponding electrical characterization. The goal of this paper is to illustrate an alternative for subdividing SF types that would otherwise be detected as triangular defects without any distinction and to show the different effects those subclasses have on finished devices with non-destructive methods that can be used in between device manufacturing steps. These results will be used as basis for further studies to confirm the found classes and to compare them with research about the different crystal structures by spectral PL measurements. For better understanding of the effect on the finished device, the PL imaging data is correlated with I-V characteristics of trenched diodes and the defect types are evaluated on their effect on the I-V characteristic, identifying 3 defect types with detrimental influence on the reverse bias and blocking voltage while the forward bias characteristic and I-V characteristic of one type is not effected by the defects.

Abstract: The quality of the epitaxial layer plays an important role in the performance of modern power electronic devices. Minority carrier lifetime is known to be sensitive to defects like dislocations, stacking faults, and points defects. Therefore, in this work lifetime measurements by microwave detected photoconductivity decay are used to evaluate the quality of the epitaxial layer on various 4H-SiC substrates from different vendors. The stability of the measurement technique is shown by a daily release measurement. This allows for a reliable analysis of almost 300 typical 1,200 V epilayer stacks. It has been shown that the effective lifetime of these samples can be separated into two different ranges. The lifetime values of about 120 ns fit to theoretical calculations. The cause for the increased lifetime of about 250 ns in the second range has yet to be determined in further research. Furthermore, the lifetime maps were used to locate defects in the surface near regions.

Abstract: In this work we present the results of a comparison between the non-contact corona-based QUAD (Quality, Uniformity and Defects) technique for inline mapping of electrically active defects in SiC epi and final wafer level electrical device data on merged PiN Schottky diodes. A new defect analysis method for the QUAD mapping is introduced that involves the creation of a die yield bin map using the in-die values of depletion voltage that facilitates the comparison to the wafer level final electrical device data. Excellent correlation of the QUAD wafer bin map results to the final wafer level electrical device data was observed, illustrating that QUAD mapping of defects in SiC epi can provide a powerful and convenient inline complement to UVPL measurements for determining which defects are electrically active and will impact device performance.

Abstract: Engineered SiC wafers with a thin 4H-SiC layer bonded on a polycrystalline carrier substrate for the application as substrate in epitaxy are investigated. Epitaxial layers grown on such substrates in 150 mm and 200 mm diameter are compared to those on state-of-the-art conventional substrates from different vendors. The performance of the engineered wafers is judged by doping and thickness uniformities as well as the number and statistics of killer defects in the epitaxial layer.

Abstract: For the ongoing commercialization of power devices based on 4H-SiC, increasing the yield and improving the reliability of these devices is becoming more and more important. In this investigation, gate oxide on 4H-SiC was examined by time-zero dielectric breakdown (TZDB) and constant current stress (CCS) time-dependent dielectric breakdown (TDDB) method in order to get insights into the influence of the epitaxial defects on the gate oxide performance and reliability. For that purpose, MOS capacitors with different gate oxides have been fabricated. Crystal defects in the epitaxial layers have been detected and mapped by ultraviolet photoluminescence (UVPL) and interference contrast (DIC) imaging. The results of the comparison of electrical data and surface mapping data indicate a negative influence on the leakage current behavior for some extended epitaxial defects. Results from TDDB measurement indicated numerous extrinsic defects, which can be traced back to gate oxide processing conditions and defect densities.

Abstract: The feasibility of thin 4H-SiC layers bonded on an alternative carrier substrate for the application as substrate in SiC epitaxy is investigated. Epitaxial layers grown on such substrates are compared to those on state-of-the-art conventional substrates from different sources. The performance of the substrates is judged by the occurrence of killer defects in the epitaxial layer as analyzed using a PL scanning tool. Additional investigations on the material properties were carried out using X-ray topography and Atomic Force Microscopy, yielding information on the crystallinity, the lattice curvature, and the surface properties of the epitaxial layers.