Papers by Author: Craig Capell

Abstract: Due to their fast switching speed, knee-free forward characteristics, and a robust, low reverse recovery body diode, SiC MOSFETs are ideal candidates to replace silicon IGBTs in many high-power medium-voltage applications. 1700 V SiC MOSFETs have already been released to production at Wolfspeed based on its 2^nd Gen technology. In this paper, we present our latest results in high voltage 4H-SiC MOSFET development. A low specific on-resistance of 4.7 mΩ⋅cm² has been achieved on 1700 V, 20 mΩ 4H-SiC DMOSFETs at 250°C based on a 3^rd generation planar MOSFET platform, which is less than half of the resistance of the previous generation devices. A detailed analysis has been carried out with respect to the static and dynamic characteristics, third quadrant conduction, and body diode reverse recovery charge, etc.

Abstract: The impact of the lifetime enhancement process using high temperature thermal oxidation method on 4H-SiC P-GTOs was investigated. 15 kV 4H-SiC P-GTOs with 140 μm thick drift layers, with and without 1450°C lifetime enhancement oxidation (LEO) process, were compared. The LEO process increased the average carrier lifetime in p-type epi layer from 0.9 μs to 6.25 μs, and it was observed that the effectiveness of the lifetime enhancement process was very sensitive to the doping concentration. The device with the LEO process showed a significant reduction in forward voltage drop and a substantially lower holding current, as expected from the carrier lifetime measurements. However, a slight reduction in blocking capability was also observed from the devices treated with LEO process. The common emitter current gain (β) of the wide base test NPN BJT was approximately 10X higher for the wafer with LEO process.

Abstract: A 1 cm x 1 cm 4H-SiC N-IGBT exhibited a blocking voltage of 20.7 kV with a leakage current of 140 μA, which represents the highest blocking voltage reported from a semiconductor power switching device to this date. The device used a 160 μm thick drift layer and a 1 μm thick Field-Stop buffer layer, and showed a V_F of 6.4 V at an I_C of 20 A, and a differential R_on,sp of 28 mΩ-cm². Switching measurements with a supply voltage of 8 kV were performed, and a turn-off time of 1.1 μs and turn-off losses of 10.9 mJ were measured at 25°C, for a 8.4 mm x 8.4 mm device with 140 μm drift layer and 2 μm F-S buffer layer. The turn-off losses were reduced by approximately 50% by using a 5 μm F-S buffer layer. A 55 kW, 1.7 kV to 7 kV boost converter operating at 5 kHz was demonstrated using the 4H-SiC N-IGBT, and an efficiency value of 97.8% was reported.

Abstract: For the first time, a 1200 V 4H-SiC power MOSFET with a monolithically integrated gate buffer circuit has been demonstrated successfully. The device used a 6x10¹⁵ cm^-3 doped, 10 μm thick n-type drift layer to support 1200 V. The gate buffer circuit was built in a p-well, formed by boron ion implantation. The integrated device provided sufficient voltage isolation for the control circuit from the drain of the power MOSFET, and supported internal supply voltages up to 20 V. The operation of the integrated devices was demonstrated. A specific on-resistance (R_on,sp) of 20 mΩ-cm² was observed. The high R_on,sp was due to the limitations in NMOS pull-up circuit topology and the body effect in the 4H-SiC NMOSFET. Development of PMOS pull-up devices is recommended for future integration efforts.

Abstract: In this work, we report our recently developed 16 kV, 1 cm², 4H-SiC PiN diode results. The SiC PiN diode was built on a 120 µm, 2×10¹⁴/cm³ doped n-type SiC drift layer with a device active area of 0.5175 cm². Forward conduction of the PiN diode was characterized at temperatures from 20°C to 200°C. At high injection-current density (J_F) of 350 ~ 400 A/cm², the differential on-resistance (R_ON,diff) of the SiC PiN diode decreased from 6.08 mΩ·cm² at 20°C to 5.12 mΩ·cm² at 200°C, resulting in a very small average temperature coefficient of –5.33 µΩ·cm²/°C, while the forward voltage drop (V_F) at 100 A/cm² reduced from 4.77 V at 20°C to 4.17 V at 200°C. This is due to an increasing high-level carrier lifetime with an increase in temperature, resulting in reduced forward voltage drop. We also observed lower R_ON,diff at higher injection-current densities, suggesting that a higher carrier lifetime is needed in this lightly doped n-type SiC thick epi-layer in order to achieve full conductivity modulation. The anode to cathode reverse blocking leakage current was measured as 0.9 µA at 16 kV at room temperature.

Abstract: In this paper, we report our recently developed 1 cm², 15 kV SiC p-GTO with an extremely low differential on-resistance (_RON,diff) of 4.08 mΩ•cm² at a high injection-current density (J_AK) of 600 ~ 710 A/cm². The 15 kV SiC p-GTO was built on a 120 μm, 2×10¹⁴/cm³ doped p-type SiC drift layer with a device active area of 0.521 cm². Forward conduction of the 15 kV SiC p-GTO was characterized at 20°C and 200°C. Over this temperature range, the R_ON,diff at J_AK of 600 ~ 710 A/cm² decreased from 4.08 mΩ•cm² at 20°C to 3.45 mΩ•cm² at J_AK of 600 ~ 680 A/cm² at 200°C. The gate to cathode blocking voltage (V_GK) was measured using a customized high-voltage test set-up. The leakage current at a V_GK of 15 kV were measured 0.25 µA and 0.41 µA at 20°C and 200°C respectively.

Abstract: The latest developments in ultra high voltage 4H-SiC IGBTs are presented. A 4H-SiC P-IGBT, with a chip size of 8.4 mm x 8.4 mm and an active area of 0.32 cm², which is double the active area of the previously reported devices [1], exhibited a blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 41 mΩ-cm² with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 17 kV, and demonstrated a room temperature differential specific on-resistance of 25.6 mΩ-cm² with a gate bias of 20 V. Field-Stop buffer layer design was used to control the charge injection from the backside. A comparison between N- and P- IGBTs, and the effects of different buffer designs, are presented.

Abstract: We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 6.7 mm x 6.7 mm 4H-SiC N-IGBT with an active area of 0.16 cm2 showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. A 4H-SiC P-IGBT exhibited a record high blocking voltage of 15 kV, while showing a differential specific on-resistance of 24 mΩ-cm2. A comparison between P- and N- IGBTs in 4H-SiC is provided in this paper.

Abstract: We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.

Abstract: In this paper, for the first time, we report 12 kV, 1 cm² SiC GTOs demonstrated with a novel negative bevel termination, which improves the breakdown voltage by >3.5 kV compared to the conventional multiple-zone Junction Termination Extension (JTE). The significant improvement in the blocking voltage was attributed to the elimination of the electrical field crowding in the periphery of the mesa with conventional JTE termination. This new termination has been used in both electrically and optically triggered SiC GTOs. An ultrafast turn-on speed of 70 ns has been measured on 12 kV, 1 cm² SiC light triggered GTOs.