Papers by Author: Fabrizio Roccaforte

Abstract: In this work, the electrical properties of Mo₂C/4H-SiC Schottky contacts were studied at different annealing temperatures. In particular, the Schottky barrier height was derived by current-voltage measurements on as-deposited and 400 °C and 700 °C-annealed contacts. The Schottky barrier height was comparable for the as-deposited and 400°C-annealed Mo₂C/4H-SiC contact (0.94 and 0.96 eV, respectively), while it increased (1.07 eV) for the 700 °C-annealed Mo₂C/4H-SiC one. For the sample annealed at 700°C, the electrical characterization of the diodes was combined with the study of the surface and interface electrical properties, by Kelvin-probe force microscopy (KPFM) and frequency dependent capacitance-voltage measurements (C-f-V) and discussed assuming a Mo/4H-SiC Schottky contact (F_B =1.39 eV) as a reference. The KPFM measurements revealed a similar value of the surface potential, thus suggesting that the work function of the metal is the same in both cases. On the other hand, a higher density of interface state was obtained by C-f-V for the Mo₂C/4H-SiC system. This latter can explain the reduction of the Schottky barrier height observed for this system.

Abstract: Silicon carbide (SiC) has emerged as a leading material for high-power applications. However, the high density of interface states (D_it) at the SiO₂/SiC interface still constrains the performance and reliability of MOSFET devices. In this work, lateral 4H-SiC MOSFETs subjected to post-deposition annealing (PDA) in nitric oxide (NO) of different durations were investigated through capacitance-voltage measurements, supported by an analytical model and an iterative MATLAB-based D_it extraction algorithm. The results demonstrate that NO PDA effectively reduces D_it not only near the conduction band edge but also towards the valence band, yielding improved channel mobility (µ_FE) and enhanced threshold voltage stability.

Abstract: Basal plane dislocations (BPDs) represent one of the most detrimental defects in 4H-SiC epitaxial wafers, causing forward voltage degradation in bipolar and power FET devices through the formation and expansion of Shockley-type stacking faults (SSFs). This expansion is driven by the recombination-enhanced dislocation glide (REDG) mechanism during forward bias operation. Despite efforts to mitigate BPD effects by converting them into threading edge dislocations (TEDs) via buffer layer engineering, throughout the epitaxial growth SSFs can still nucleate and propagate, particularly under high current injection. This work presents a comprehensive analysis combining electrical characterization, fault localization technique, Scanning Electron Microscopy (SEM) and micro-photoluminescence (μ-PL) to investigate SSF formation, crystallographic features, and their impact on device performance. The results underscore the critical role of advanced diagnostics and epitaxial process optimization in controlling SSF-related degradation and improving the reliability of SiC power devices.

Abstract: This paper reports on the effect of a sulfurization thermal process of the silicon carbide surface on the properties of Ni/4H-SiC Schottky barrier. In particular, the incorporation of sulfur (S) in the 4H-SiC near-surface region was observed at the process performed at 800 °C, without any significant effect on the surface morphology. On the other hand, Ni/4H-SiC Schottky contacts fabricated on the sulfurized 4H-SiC surface showed a 0.3 eV reduction of the average barrier height with a narrower distribution, with respect to the untreated sample. These results were explained by an increase of the 4H-SiC electron affinity after sulfurization, and a Fermi level pinning effect.

Abstract: In this work, we investigated the electrical properties evolution of Mo/4H-SiC Schottky contacts following thermal annealing treatments at temperature up to 950 °C. The electrical characterization under forward and reverse bias revealed a reduction of the barrier height from 1.45 eV (as-deposited contact) to 1.30 eV (950°C-annealed contact), with the presence of inhomogeneity in the contact, while the leakage current followed a thermionic-field emission (TFE) model after annealing at 750 °C and presented a significant increase for the 950°C-annealed contact. The electrical characterization was associated with microstructural analyses, which highlighted an enlargement of the grains forming the structure of the Mo-film and the presence of voids near the Mo/4H-SiC interface. These observations can be at the base of the variation in the electrical behavior of the contact.

Abstract: In this paper, we report on the growth of highly uniform MoS₂ films, mostly consisting of monolayers, on SiC surfaces with different doping levels (n- SiC epitaxy, ~10¹⁶ cm^-3, and n⁺ SiC substrate, ~10¹⁹ cm^-3) by sulfurization of a pre-deposited ultra-thin MoO_x films. MoS₂ layers are lowly strained (~0.12% tensile strain) and highly p-type doped (<N_h>≈4×10¹⁹ cm⁻³), due to MoO₃ residues still present after the sulfurization process. Nanoscale resolution I-V analyses by conductive atomic force microscopy (C-AFM) show a strongly rectifying behavior for MoS₂ junction with n^- SiC, whereas the p⁺ MoS₂/n⁺ SiC junction exhibits an enhanced reverse current and a negative differential behavior under forward bias. This latter observation, indicating the occurrence of band-to-band-tunneling from the occupied states of n⁺ SiC conduction band to the empty states of p⁺ MoS₂ valence band, is a confirmation of the very sharp hetero-interface between the two materials. These results pave the way to the fabrication of ultra-fast switching Esaki diodes on 4H-SiC.

Abstract: In this work, we investigated the impact of crystallographic defects (specifically stacking faults, SFs) on the mechanisms of the current transport in 4H-SiC Schottky contacts. The electrical characteristics were studied under both forward and reverse bias. In particular, while the presence of SFs under the contact did not show a significant impact on the forward characteristics of the Schottky diode, a significant increase in the leakage current occurred under reverse bias in defective diodes. This anomalous behavior can be explained by a space-charge limited current model, consistent with the presence of a trapping state distribution in the 4H-SiC gap. An increase of the reverse bias above 30 V leads to a complete trap filling. The weak temperature-dependence of the leakage current observed at highest voltage suggests that a tunneling of the carriers through the barrier can be also present.

Abstract: New generations of SiC power devices require to be fabricated on very thin substrates, in order to significantly reduce the series resistance of the device. The role of thinning process on the formation of backside ohmic contact has been investigated in this work. Three different mechanical grinding processes have been adopted, resulting in different amounts of defectivity and surface roughness values. An excimer UV laser has been used to form a Ni-silicide based ohmic contact on the backside of the wafers. The reacted layer has been studied by means of Atomic Force Microscopy (AFM), Transmission Electron Microscopy (TEM) and X-Ray Diffraction (XRD) analyses, as a function of grinding process parameters and laser annealing conditions. The ohmic contact has been evaluated by measuring the Sheet Resistance (R_s) of silicided layers and the V_f at nominal current of Schottky Barrier Diode (SBD) devices, fabricated on 150 mm-diameter 4H-SiC wafers. A strong relationship has been found between the crystal damage, induced by thinning process, and the structural, morphological and electrical properties of silicided ohmic contact, formed by UV laser annealing, revealing that the silicide reaction is moved forward, at fixed annealing conditions, by the increasing of crystal defectivity and surface roughness of SiC.

Abstract: The suitability of scanning probe methods based on atomic force microscopy (AFM) measurements is explored to investigate with high spatial resolution the elementary cell of 4H-SiC power MOSFETs. The two-dimensional (2D) cross-sectional maps demonstrated a high spatial resolution of about 5 nm using the scanning spreading resistance microscopy (SSRM) capabilities. Furthermore, the scanning capacitance microscopy (SCM) capabilities enabled visualizing the fluctuations of charge carrier concentration across the different parts of the MOSFETs elementary cell.

Abstract: In this paper, the effect of different post oxide deposition nitridation processes in NO on n-channel lateral MOSFETs fabricated on implanted 4H-SiC were investigated. In particular, the electrical behavior of the MOSFETs was deeply investigated not only in terms of SiO₂/SiC interface state density and field effect mobility, but also considering the threshold voltage stability effect. The aim of this work was to explore to which extent post oxide deposition annealing in NO is beneficial for the MOS interface behavior and when their detrimental effects start to become predominant on the device performances. Here, the separation of the trapping states at the interface – either close to the conduction and valence band edges – and the near interface oxide traps are reported for the different duration of the post oxide deposition annealing. In fact, cyclic gate bias stress was employed in order to analyze the behavior of the trapping states and to correlate them with the variation of the benefits in terms of the channel mobility (that saturates at about 80 cm²V^-1s^-1), and on the threshold voltage instability effect. In particular, prolonged PDAs may induce an increase of the amount of trapping states close to the valence band edge and inside the insulator of about 20% and 50 %, respectively.