Authors: Andrea Severino, Domenico Mello, Simona Boninelli, Fabrizio Roccaforte, Filippo Giannazzo, Patrick Fiorenza, Cristiano Calabretta, Lucia Calcagno, Nicolo Piluso, Giuseppe Arena
Abstract: Silicon carbide (SiC) is an attractive material for power devices owing to the availability of high-quality epitaxial wafers and superior physical properties, such as its high breakdown electric field strength, high electron mobility, and low anisotropy. Ion implantation is a key process for both n- and p-type selective doping of SiC devices. A subsequent annealing in the temperature range of 1600- 1800°C is required to remove the damage induced by the implantation process and to electrically activate the implanted dopants. The aim of this work is the investigation of the effect of thermal annealing on the damage induced by Phosphorous ion implantation to produce n-type regions.
407
Authors: Monia Spera, Giuseppe Greco, Raffaella Lo Nigro, Salvatore Di Franco, Domenico Corso, Patrick Fiorenza, Filippo Giannazzo, Marcin Zielinski, Francesco La Via, Fabrizio Roccaforte
Abstract: This paper reports on the formation and characterization of Ohmic contacts to n-type and p-type type 3C-SiC layers grown on silicon substrates. In particular, Ohmic contact behavior was obtained either using Ni or Ti/Al/Ni layers annealed at 950°C. The values of the specific contact resistance ρc estimated by means of circular TLM (C-TLM) structures varied in the range ~ 10-3-10-5 Ωcm2, depending on the doping level of the 3C-SiC layer. A structural analysis performed by X-Ray Diffraction (XRD) allowed to identify the main phases formed upon annealing, i.e., Ni2Si and Al3Ni2. The morphology of the reacted contacts depended on that of the underlying substrate. The results can be useful for the development of a variety of devices on the cubic 3C-SiC polytype.
485
Authors: Patrick Fiorenza, Marilena Vivona, Ferdinando Iucolano, Andrea Severino, Simona Lorenti, Fabrizio Roccaforte
Abstract: We present a temperature-dependence electrical characterization of the oxide/semiconductor interface in MOS capacitors with a SiO2 layer deposited on 4H-SiC using dichlorosilane and nitrogen-based vapor precursors. The post deposition annealing process in N2O allowed to achieve an interface state density Dit 9.0×1011cm-2eV-1 below the conduction band edge. At room temperature, an electron barrier height (conduction band offset) of 2.8 eV was measured using the standard Fowler-Nordheim tunneling model. The electron conduction through the SiO2 insulating layer was evaluated by studying the experimental temperature dependence of the gate current. In particular, the Fowler-Nordheim electron barrier height showed a negative temperature coefficient (dφB/dT = - 0.98 meV/°C), which is very close to the expected value for an ideal SiO2/4H-SiC system. This result, obtained for deposited SiO2 layers, is an improvement compared to the values of the temperature coefficient of the Fowler-Nordheim electron barrier height reported for thermally grown SiO2. In fact, the smaller dependence of φB on the temperature observed in this work represents a clear advantage of our deposited SiO2 for the operation of MOSFET devices at high temperatures.
473
Authors: Patrick Fiorenza, Ferdinando Iucolano, Mario Saggio, Fabrizio Roccaforte
Abstract: In this paper, near interface traps (NITs) in lateral 4H-SiC MOSFETs were investigated employing temperature dependent transient gate capacitance measurements (C-t). The C-t measurements as a function of temperature indicated that the effective NITs discharge time is temperature independent and electrons from NITs are emitted toward the semiconductor via-tunnelling and/or trap-to-trap tunnelling. The NITs discharge time was modelled taking into account also the interface state density in a distributed circuit and it allowed to locate traps within a distance of about 1.3nm from the SiO2/4H-SiC interface.
285
Authors: Francesco La Via, Fabrizio Roccaforte, Antonino La Magna, Roberta Nipoti, Fulvio Mancarella, Peter J. Wellmann, Danilo Crippa, Marco Mauceri, Peter Ward, Leo MIGLIO, Marcin Zielinski, Adolf Schöner, Ahmed Nejim, Laura Vivani, Rositza Yakimova, Mikael Syväjärvi, Gregory Grosset, Frank Torregrosa, Michael Jennings, Philip Andrew Mawby, Ruggero Anzalone, Salvo Coffa, Hiroyuki Nagasawa
Abstract: The cubic polytype of SiC (3C-SiC) is the only one that can be grown on silicon substrate with the thickness required for targeted applications. Possibility to grow such layers has remained for a long period a real advantage in terms of scalability. Even the relatively narrow band-gap of 3C-SiC (2.3eV), which is often regarded as detrimental in comparison with other polytypes, can in fact be an advantage. However, the crystalline quality of 3C-SiC on silicon has to be improved in order to benefit from the intrinsic 3C-SiC properties. In this project new approaches for the reduction of defects will be used and new compliance substrates that can help to reduce the stress and the defect density at the same time will be explored. Numerical simulations will be applied to optimize growth conditions and reduce stress in the material. The structure of the final devices will be simulated using the appropriated numerical tools where new numerical model will be introduced to take into account the properties of the new material. Thanks to these simulations tools and the new material with low defect density, several devices that can work at high power and with low power consumption will be realized within the project.
913
Authors: Fabrizio Roccaforte, Marilena Vivona, Giuseppe Greco, Raffaella Lo Nigro, Filippo Giannazzo, Simone Rascunà, Mario Saggio
Abstract: The physics and technology of metal/semiconductor interfaces are key-points in the development of silicon carbide (SiC) based devices. Although in the last decade, the metal to 4H-SiC contacts, either Ohmic or Schottky type, have been extensively investigated with important achievements, these remain even now an intriguing topic since metal contacts are fundamental bricks of all electronic devices. Hence, their comprehension is at the base of the improvement of the performances of simple devices and complex systems. In this context, this paper aims to highlight some relevant aspects related to metal/semiconductor contacts to SiC, both on n-type and p-type, with an emphasis on the role of the barrier and on the carrier transport mechanisms at the interfaces.
339
Authors: Marilena Vivona, Giuseppe Greco, Corrado Bongiorno, Salvatore Di Franco, Raffaella Lo Nigro, Silvia Scalese, Simone Rascunà, Mario Saggio, Fabrizio Roccaforte
Abstract: This work reports on the electrical and microstructural properties of Ti/Al/Ni contacts to p-type implanted 4H-SiC obtained by rapid thermal annealing of a metal stack of Ti (70 nm)/Al (200 nm)/Ni (50 nm). The contact characteristics were monitored at increasing value of the annealing temperature. The Ohmic behavior of the contact, with a specific contact resistance value of 2.3×10-4 Ω·cm2, is obtained for an annealing at 950 °C. The structural analyses of the contact, carried out by XRD and TEM, reveal the occurrence of reactions, with the detection of the Al3Ni2 and AlTi phases in the upper part of the contact and of an epitaxially oriented TiC layer at the interface. These reactions are considered the key factors in the formation of an Ohmic contact in our annealed Ti/Al/Ni system. The temperature-dependence study of the electrical characteristics reveals a predominant thermionic field emission (TFE) mechanism for the current conduction through the contact, with a barrier height of 0.56 eV.
377
Authors: Patrick Fiorenza, Antonino La Magna, Marilena Vivona, Filippo Giannazzo, Fabrizio Roccaforte
Abstract: This paper reports on the conduction mechanisms and trapping effects in SiO2/4H-SiC MOS-based devices subjected to post deposition annealing in N2O. In particular, the anomalous Fowler-Nordheim (FN) tunnelling through the SiO2/4H-SiC barrier observed under consecutive reverse bias sweeps was studied by temperature and time dependent gate current measurements. The excess of gate current with respect to the theoretical FN predictions was explained by a charge-discharge mechanism of Near Interface Traps (NITs) in the oxide. The gate current transient was described with a semi-empirical analytical model, modifying the standard FN model with a time-dependent electric field to account for the neutralization of trapped charges at NITs.
123
Authors: Marilena Vivona, Patrick Fiorenza, Ferdinando Iucolano, Andrea Severino, Simona Lorenti, Fabrizio Roccaforte
Abstract: This work reports on the physical and electrical characterization of the oxide/semiconductor interface in MOS capacitors with the SiO2 layer deposited by a high temperature process from dichlorosilane and nitrogen-based vapor precursors and subjected to a post deposition annealing process in N2O. Low interface state density (Dit ≈ 9.0×1011cm-2eV-1) was found at 0.2 eV from EC, which is comparable to the values typically obtained in other lower temperature deposited oxides (e.g., TEOS). A barrier height of 2.8 eV was derived from the Fowler-Nordheim plot, very close to the ideal value expected for SiO2/4H-SiC interface. Basing on these preliminary results, the integration in MOSFETs devices can be envisaged.
331
Authors: Antonino La Magna, Ioannis Deretzis, Filippo Giannazzo, Giuseppe Nicotra, Fabrizio Roccaforte, Corrado Spinella, Rositza Yakimova
Abstract: A Kinetic Monte Carlo scheme is applied to simulate with atomic resolution the synthesis of mono (few) layer(s) graphene (Gr) from a silicon carbide (SiC) substrate by selective evaporation of silicon (Si) atoms. The simulation computes the individual dynamics of the residual carbon (C) atoms which diffuse and reconfigure starting from the positions occupied in the SiC hexagonal lattice to the final Gr honeycomb structure. During the transition they gradually modify hybridization (from sp3 to sp2) and bond partners (from Si-C to C-C). We demonstrate that our method is able to recover the complex evolution steps of the epitaxial Gr on SiC in large systems for large time intervals. Moreover, the simulation results can be validated directly by means of comparison with experimental data when varying the material (e.g. initial surface configuration or polarity) or process (e.g. temperature and pressure) conditions.
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