Papers by Author: Farid Sebaai

Abstract: Formulated chemical ACT^® SG6xxx series demonstrated SiGe etching selective to SiGe with lower Ge concentration. SiGe etching rate on SiGe/Si multi-stack shown steep trend as a function of Ge concentration, resulting in 338 of selectivity between SiGe30% and SiGe15%. Also, apparent loss on SiN and SiO₂ was not observed. Moreover, SiGe etch rate was not impacted by chemical flow in the beaker. It suggests reaction-controlled based etching, which leads to good within wafer uniformity in etching rate of 300mm wafer spin processing. In conclusion, ACT^® SG6xxx series is a promising option for the formation of BDI/MDIs in Nanosheet, Forksheet and CFET.

Abstract: Test structure development is critical for single wafer pattern collapse evaluations. A good test vehicle not only allows optimization and benchmarking of different processes, but also facilitates understanding of the underlying mechanism. For high aspect ratio silicon nanopillar arrays, by increasing the gap distance in one direction while keeping the other direction constant, an unexpected higher collapse rate is found. This preliminary finding is contradictory to the prevalent models that are based on equilibrium force balance between capillary and mechanical interactions. It is postulated that the asymmetric arrangement of pillars facilitates the formation of liquid bridge and thus more pattern collapse. Such test structures can bring useful insights to understand the dynamic mechanism of pattern collapse.

Abstract: Thermally activated ozone gas (TAO) was demonstrated as an alternative technology to conventional spin-on carbon (SOC) stripping. The SOC stripping rate with ozone gas was found to be a function of substrate temperature and actual ozone amount calculated from the ozone flow rate and concentration. Furthermore, work function metal (WFM) stripping rate showed a high selectivity to SOC films, and the amount of oxidation TiN, which is a WFM metal, was also equivalent to conventional technology of SOC stripping. This TAO gas process can be used in clean tools, making it a promising integrated solution for SOC stripping followed by post clean.

Abstract: This paper addresses challenges and solutions of replacement metal gate of gate-all-around nanosheet devices. The unit process and integration solutions for the metal gate patterning as well as interface dipole patterning to offer multiple threshold voltage have been developed. The challenges of long channel device integration are also discussed.

Abstract: The continuous down scaling of the dimensions for the logic devices has imposed to carefully track the pattern collapse issue when cleaning after FIN etch. Showing the limitations of the hot IPA drying technique toward scaled FIN dimensions, a cleaning using a surface modification drying technique has been proposed and successfully implemented. It is also discussed the use of some post treatment solutions to remove the grafted layer used to modify the FIN surface while preserving the integrity of the FIN structures.

Abstract: Gate All-Around (GAA) is considered a key design feature for future CMOS technology. SiGe vs. Si selective etch is required for Si nanowire formation in GAA. It is confirmed the selective SiGe removal with commodity chemical (mixtures of hydrofluoric acid (HF), hydrogen peroxide (H2O2) and acetic acid (CH3COOH, HAc)), however the thick oxidized layer on Si NW was observed after commodity chemical process, which is indicated the significant Si NW loss. On the other hand, the formulated mixture ACT® SG-101, which is focusing on SiGe oxidizer, chemical pH, solvent polarity & corrosion inhibitor for chemical concept, was performed higher selectivity and lower Si loss than commodity chemical. The formulated mixture has also been used to form an inner spacer for cavity etch scheme and confirmed uniform cavity etch and inner spacer filling on topological test structure.

Abstract: Over the past decade, many advanced drying techniques have been developed to reduce and prevent pattern collapse of high aspect ratio (HAR) structures after wet processing. However, different dimensions, profiles and materials of HAR structures used in literature make it difficult to compare the efficiency of different drying processes. In this work, standard 300 mm wafer test structures, characterization and analysis techniques have been developed for quantitative analysis of pattern collapse rate as a function of the intrinsic mechanical property of HAR structures. Such standardized single wafer evaluations are important for benchmarking different drying techniques.

Abstract: A selective wet etching process for fabricating SiGe and Ge nanowires for gate all around transistors is introduced in this paper. Two formulated proprietary chemical mixtures with highly selective etching properties (Si vs. SiGe and SiGe vs. Ge) can effectively dissolve the sacrificial layers with minimal damage to the interstitial nanowire materials. The Auger Electron Spectroscopy (AES) surface characterization indicates that no chemical contamination is left after the wet etching process.

Abstract: A new method is proposed for the formation of Ge nanowires in a gate-all-around integration scheme. We combine the use of GeSn:P/Ge epitaxial stacks and low-temperature Cl₂ vapor-phase etching to demonstrate a high etch selectivity of GeSn:P versus Ge. The process can be combined with an in situ passivation of the Ge nanowires, which can bring several advantages in view of improved process reliability and control.

Abstract: For the Ge nanowire formation in a gate-all-around (GAA) integration scheme, a selective etch of Si_0.5Ge_0.5 or Si_0.3Ge_0.7 selective to Ge is considered. Two wet process approaches were evaluated: a boiling TMAH as a commodity chemistry is compared with a formulated chemistry using a multi-stack SiGe/Ge layer as a test vehicle. The boiling TMAH exhibits an anisotropic etch of the SiGe whereas the formulated semi-aqueous chemistry removes the sacrificial SiGe by an isotropic etch which makes the process suitable for a Ge nanowire release process.