Papers by Author: Francesco La Via

Abstract: This paper reports on the formation and characterization of Ohmic contacts to n-type and p-type type 3C-SiC layers grown on silicon substrates. In particular, Ohmic contact behavior was obtained either using Ni or Ti/Al/Ni layers annealed at 950°C. The values of the specific contact resistance ρ_c estimated by means of circular TLM (C-TLM) structures varied in the range ~ 10^-3-10^-5 Ωcm², depending on the doping level of the 3C-SiC layer. A structural analysis performed by X-Ray Diffraction (XRD) allowed to identify the main phases formed upon annealing, i.e., Ni₂Si and Al₃Ni₂. The morphology of the reacted contacts depended on that of the underlying substrate. The results can be useful for the development of a variety of devices on the cubic 3C-SiC polytype.

Abstract: Thermal annealing plays a crucial role for healing the defectiveness in the ion implanted regions of DIMOSFETs (Double Implanted MOSFETs) devices. In this work, we have studied the effect of a double step annealing on the body (Al implanted) and the source (P implanted) regions of such devices. We found that a high temperature annealing (1750°C, 1h) followed by a lower temperature one (1500°C, 4h) is mandatory to achieve low defects concentration and good crystal quality in both the n-and p-type zones of the device.

Abstract: Stacking Faults (SFs) are the main defect of 3C-SiC material and in this work a detailed study of this typology of defect is presented. We studied the behavior of SFs with High Resolution XRD and STEM analysis. The homo-epitaxial growth was proposed as a solution for the reduction of SFs density in 3C-SiC material and the influence of the growth condition on the SFs density was studied. The knowledge of the mechanism of SFs reduction is crucial for the development of a high quality material for devices fabrication.

Abstract: The cubic polytype of SiC (3C-SiC) is the only one that can be grown on silicon substrate with the thickness required for targeted applications. Possibility to grow such layers has remained for a long period a real advantage in terms of scalability. Even the relatively narrow band-gap of 3C-SiC (2.3eV), which is often regarded as detrimental in comparison with other polytypes, can in fact be an advantage. However, the crystalline quality of 3C-SiC on silicon has to be improved in order to benefit from the intrinsic 3C-SiC properties. In this project new approaches for the reduction of defects will be used and new compliance substrates that can help to reduce the stress and the defect density at the same time will be explored. Numerical simulations will be applied to optimize growth conditions and reduce stress in the material. The structure of the final devices will be simulated using the appropriated numerical tools where new numerical model will be introduced to take into account the properties of the new material. Thanks to these simulations tools and the new material with low defect density, several devices that can work at high power and with low power consumption will be realized within the project.

Abstract: In this work the deposition of buffer layer has been studied in order to increase the quality of the epitaxial layer and improve the performance of device. The comparison between two different thicknesses of buffer layer reveals a decrease of crystallographic defects and an improvement of electrical parameters of MOSFET device as leakage current and breakdown voltage.

Abstract: In this work a comparison between different 6 inches 4H-SiC commercial substrates after post processing has been shown. The main comparison was done between two different suppliers after a thinning process that leaves the sample with a final thickness of 150 microns. After the processing the two substrates show different behavior with different curvature and residual stress. X-Ray diffraction show different crystal quality and curvature values of the substrates. Micro-Raman show different residual stress of the substrates before and after the thinning process. Moreover, molten KOH etching for dislocation detection also show different value of dislocation density for both substrates.

Abstract: We report on the growth of bulk 3C-SiC by sublimation on epitaxial seeding layers (3C-SiC/Si) from chemical vapor deposition. We have reached a materials thickness of 0.85 mm and an area of 10.5 cm² which can be enlarged further. The high crystalline quality is characterized by the absence of secondary polytype inclusions and the absence double position grain boundaries.

Abstract: A new technique with micro-Raman and micro-PL analysis is proposed to detect defects in 3C-SiC epitaxial films. The high-power of an above band-gap laser is used to increase locally the free carriers density in un-doped epitaxial material (n < 10¹⁶ cm^-3). The electronic plasma couples with the longitudinal optical (LO) Raman mode determining the so-called LOPC effect. The Raman shift of the LO phonon-plasmon-coupled mode (LOPC) changes as the free carriers density is modified. Crystallographic defects induce a modification of the free carriers density determining a change in the Raman shift of LO mode and in the PL emission from the 3C-SiC gap. Thus we suppose that the results observed are connected to crystallographic defects and we propose this technique as a methodology to analyze extended defects in 3C-SiC material because a detailed study of defects in 3C-SiC has not yet been performed.

Abstract: 4H-SiC defects evolution after thermal processes has been evaluated. Different annealing temperatures have been used to decrease the defect density of epitaxial layer (as stacking faults) and recover the damage occurred after ion implantation. The propagation of defects has been detected by Photoluminescence tool and monitored during the thermal processes. The results show that implants do not affect the surface roughness and how a preliminary annealing process, before ion implantation step, can be useful in order to reduce the SFs density. It shown the effect of tuned thermal process. A kind of defect, generated by implant and subsequent annealing, can be removed by an appropriate thermal budget, while others can increase. A fine tuning of thermal process parameters, temperature and timing, is useful to recover the crystallographic quality of the epilayer and increase the yield of the power device.

Abstract: The growth morphology of epitaxial 3C-SiC crystals grown on hexagonal pillars deeply etched into Si (111) substrates is presented. Different growth velocities of side facets let the top crystal facet evolve from hexagonal towards triangular shape during growth. The lateral size and separation between Si pillars determine the onset of fusion between neighboring crystals during growth at a height tailoring of which is crucial to reduce the stacking fault (SF) density of the coalesced surface. Intermediate partial fusion of neighboring crystals is shown as well as a surface of fully coalesced crystals.