Papers by Author: Gabriel Ferro

Abstract: Because the well-known site-competition and step-controlled epitaxy rules cannot reasonably describe all the incorporation processes of the main impurities (Al and N) into 4H-SiC during epitaxy, the concept of replacement incorporation was proposed and applied to explain the experimental results published so far. In this model, the transient formation of C or Si vacancies at the surface or sub-surface of terraces is proposed to play a key role by destabilizing the impurities sitting on them. In addition to the availability of these vacancies at the surface, desorption was proposed to be a very important limiting process for Al incorporation while only occasionally relevant for N incorporation. The main 4H-SiC epitaxial growth parameters are reviewed and discussed according to the proposed replacement model.

Abstract: We report for the first time the successful heteroepitaxial growth of Si(100) oriented layer on top of a 3C-SiC(001) seed. By using a post-growth modification of the 3C-SiC surface (pulse insertion of precursors during cooling), it led to a change in Si nucleation, favoring squared (100) islands instead of elongated (110) ones. Without this surface modification step, the Si layers grown on 3C-SiC were always polycrystalline with a mixture of (110) and (100) orientations. Using such Si(100) layer grown on top of 3C-SiC(100), a (100) oriented 3C-SiC single crystalline layer was successfully grown on top, fabricating thus for the first time a fully (100) oriented multilayer heterostructure made of Si_(substrate)/SiC/Si/SiC.

Abstract: This study deals with the electrical characterization of PiN diodes fabricated on a 4°off-axis 4H-SiC n⁺ substrate with a n^- epilayer (1×10¹⁶ cm^-3 / 10 µm). Optimized p⁺⁺ epitaxial areas were grown by Vapour-Liquid-Solid (VLS) transport to form p⁺ emitters localized in etched wells with 1 µm depth. Incorporated Al level in the VLS p⁺⁺ zones was checked by SIMS (Secondary Ion Mass Spectroscopy), and the doping level was found in the range of 1-3×10²⁰ at.cm^-3. Electrical characterizations were performed on these PiN diodes, with 800 nm deposit of aluminium as ohmic contact on p-type SiC. Electrical measurements show a bipolar behaviour, and very high sustainable forward current densities ≥ 3 kA.cm^-2, preserving a low leakage current density in reverse bias. These measurements were obtained on structures without any passivation and no edge termination.

Abstract: In this study, we compare the electrical properties of MOS capacitors fabricated on different surface morphologies. Comparing a standard, low-roughness (<1nm), surface with one with a roughness of ~40nm, characterized by big macrosteps and large terraces. We compared the two surfaces for different thermal oxide thicknesses, ranging from d_Ox = 3.6 nm to d_Ox = 32 nm. The extracted interface state traps (D_it) shows a small, but systematic, decrease of ~10-15 % for the samples with macrosteps.

Abstract: Silicon deposition on 3C-SiC seeds was studied as a function of seed orientations and thicknesses. The 3C-SiC seeds were grown on silicon substrates of (100), (110), (111) and (211) orientations by standard two-step CVD (low temperature carbonization followed by high temperature epitaxy). Then, the Si layers were grown onto these SiC seeds at various temperatures. Almost all the conditions gave polycrystalline deposit. At high deposition temperature (1350°C) the Si deposit was composed of separated hillocks and was never fully covering the 3C-SiC seeds. Lower deposition temperatures (≤ 1100°C) allowed obtaining silicon full coverage but not full epitaxy. Focusing on (100) orientation, it was shown that (100) Si deposit could be obtained but only on the as carbonized 3C-SiC sample, i.e. with the thinner SiC layer.

Abstract: In this study, the electrical properties of Ti₃SiC₂ based ohmic contacts formed on p-type 4H-SiC(0001) 4°-off substrates were studied. The Ti₃SiC₂ thin films were grown by thermal annealing (from 900°C to 1200°C) of Ti₅₀Al₅₀ layer deposited by magnetron sputtering. XRD analyzes were performed on the samples to further investigate the compounds formed after annealing. Using TLM structures, the Specific Contact Resistance (SCR) at room temperature of all contacts was measured. The temperature dependence (up to 600°C) of the SCR was studied to understand the current mechanisms at the interface and to determine the barrier height value by fitting the experimental results using the thermionic field emission theory. Aging tests showed that Ti₃SiC₂ based contacts were stable up to 200h at 600°C under Ar.

Abstract: This work reports on the CVD heteroepitaxial growth of 3C-SiC layers on diamond (100) substrates. To obtain good layer quality, the growth procedure involves a “silicidation” step consisting in depositing a silicon layer by CVD on the diamond substrate, in order to elaborate a very thin SiC buffer layer. 3C-SiC growth is then performed on this SiC seeding layer. Silicidation and growth parameters have been studied in order to improve the quality and the morphology uniformity of the heteroepitaxial layer. The study points out the role of liquid silicon during the growth process.

Abstract: P/N junctions have been fabricated with N⁺ commercial 4H-SiC substrate on which Vapor-Liquid-Solid (VLS) selective epitaxy was used to create a localized p-type doping. The influence of the carrier gas nature (argon or hydrogen) has been investigated in terms of quality of the growth morphology, deposit thickness and electrical behavior of the P/N junction. Distinct results have been observed with a clear improvement when using VLS selective epitaxy under hydrogen.

Abstract: The aim of this study was to find conditions allowing the "natural" formation of a regular and controllable step bunched morphology on a 4H-SiC seed without the need of any SiC deposition. This was performed by melting a bulk piece of Si on a 4°off 4H seed in the temperature range of 1500 - 1600°C, for 15 min. After etching the remaining Si, the 4H surface was found to be successfully highly step bunched with steps very parallel and regular. A mechanism of dissolution-precipitation was proposed, which could occur both on a short (step to step) and long (centre to periphery) range. This process is kinetically limited at low temperature (1500-1550°C) and considered to be close to the equilibrium at 1600°C.

Abstract: We fabricated and characterized record small microdisk resonators in thin (210 nm) 3C-SiC film grown on Si (100) substrate. It was found to support high quality factor whispering gallery modes at visible wavelengths. We demonstrated room temperature coupling of these modes to the intrinsic photoluminescence of 3C-SiC at room temperatures and identified their polarization. Finally, we discussed applications for quasi-phasematched second harmonic generation from infrared visible wavelengths.