Papers by Author: Geert Doumen

Abstract: This work focuses on capillary-induced collapse of high-aspect-ratio silicon nanopillars. Modification of the surface chemistry is demonstrated to be an efficient approach for reducing capillary forces and consequently reduce pattern collapse. Special effort is spent on determination of the wetting state of chemically modified surfaces as complete structure wetting is of utmost importance in wet processing. In light of this, an ATR-FTIR based method has been developed to unambiguously distinguish between wetting and non-wetting states.

Abstract: With the downscaling of devices, due to device geometry shrinkage, the total number of cleaning steps has increased dramatically. As a result, the number of drying cycles after cleaning has increased as well. As the device shrinks with the integration density increase, it is noteworthy that a perfect drying efficiency is mandatory to obtain a high performance device [. Basically, the mechanism of wafer drying in semiconductor industry can be explained as: first reducing the amount of liquid on the wafer surface by mechanical forces. There are some approaches for removing the liquid such as spinning, high pressure gas blowing by nozzle or air-jet, vertical withdrawal from the liquid bath, using surface gradient tension and so on [2]. Second: if the mechanical forces in the liquid removal part are not sufficient for drying and some droplets or a thin liquid layer remain on the wafer surface, complete drying will be achieved by evaporation of the remaining layer on the wafer. After this evaporation step, known as state transformation, the wafers will be completely dried. Evaporation of the remaining liquid layer is the main mechanism for generating drying defects (watermarks, residues, particles, and etc.)[3]. In this study, we propose a new methodology for semiconductor wafer drying based on a high-pressure gas flow. In comparison to conventional drying tools, the new drying set up combines high speed drying (wafer drying time down to 2 sec at 150mm.s^-1) and a low number of added drying defects.

Abstract: Following Moores scaling law, the transistor source and drain area become shallower and higher doped regions. As a consequence the limitations of substrate and dopant loss during cleaning become more stringent. For a better understanding, highly B, As and P doped blanket substrates, either prepared by ion implantation or by EPI growth, are studied. Substrate and dopant loss as a function of time and different HF etching conditions is monitored by Inductively Coupled Plasma Mass Spectrometry (ICP-MS) and additional techniques like Spectroscopic Ellipsometry (SE), .... It is shown that in general, the Si etching is dependent of the position of the Fermi level. More remarkably, the junction (4 nm) of a non-annealed heavily As or P doped substrate is completely removed after less than 20 min of etching in HF. This process is related to enhanced etch rates because of the amorphization of the substrate.