Papers by Author: Gil Yong Chung

Abstract: Epilayers grown on substrates etched by various etching conditions were studied for stacking fault defects. Substrates were etched by H₂, H₂+ HCl and H₂ + C_xH_y gases prior to epilayer growth for comparison. High density of SF was observed in the epilayers when H₂+HCl or H₂+C_xH_y gas mixtures were used. On the other hand, much lower density of stacking faults (SF) (<1 cm^-2) was observed in the epilayer grown on the surface etched by only H₂ gas. However, a high number of pits were generated in the epilayer grown on substrate etched by H₂ only, which can be considered to be tradeoff of achieving low SF in epilayer by substrate etching. We also conclude from our experimental results that C rich surface is more favorable to generate SF in epilayer compared to Si rich surface.

Abstract: Shifts in the spatial distribution of threading dislocations in 150 mm 4H SiC wafers were examined as a response to intentional changes in both the flow of the nitrogen source gas used to control resistivity during bulk crystal growth, and the growth rate. The density of threading edge and screw dislocations was found to be more evenly distributed in wafers produced under a high-growth rate, low-resistivity process. This result corresponded to a flattening of the resistivity distribution, and a ~34% reduction in on-and off-facet resistivity differential. The effect was attributed to regularized 4H island coalescence due to modulation of step terrace width.

Abstract: The impact of surface stress due to polish and grind processes on wafer bow was studied as a function of abrasive size. Results indicate that sub-surface damage from these processes can introduce significant surface stress. For polishing processes, this stress is proportional to mean abrasive size. The study also investigates stress as a function of depth below the wafer surface and finds that most stress is concentrated near the wafer surface.

Abstract: Continuous optimization of bulk 4H SiC PVT crystal growth processes has yielded an improvement in 150 mm wafer shape, as well as a marked reduction in stacking fault density. Mean wafer bow and warp decreased by 26% and 14%, respectively, while stacking faults were nearly eliminated from wafers produced using the refined process. These quality enhancements corresponded to an adjustment to key thermal parameters predicted to control intrinsic crystal stresses, and a reduction in crystal dome curvature.

Abstract: Synchrotron X-ray Topography with grazing incidence geometry is useful for discerning defects at different depths below the crystal surface, particularly for 4H-SiC epitaxial wafers. However, the penetration depths measured from X-ray topographs are much larger than the theoretical values. In order to interpret this discrepancy, we simulate topographic contrast of dislocations based on two of the most basic contrast formation mechanisms – orientation contrast and kinematical contrast. Orientation contrast considers merely the displacement fields associated with dislocations while kinematical contrast also takes the diffraction volume into account. The diffraction volume is defined by the effective misorientation around dislocations and the rocking curve width for particular diffraction vector. Ray Tracing Simulation has been carried out to visualize dislocation contrast for both models, taking into account the photoelectric absorption of X-ray beams inside the crystal. Results show that orientation contrast plays the key role in determining both the contrast and X-ray penetration depths for different types of dislocations.

Abstract: Synchrotron white beam X-ray topography studies carried out on 4H-SiC wafers characterized by locally varying doping concentrations reveals the presence of overlapping Shockley stacking faults generated from residual surface scratches in regions of higher doping concentrations after the wafers have been subjected to heat treatment. The fault generation process is driven by the fact that in regions of higher doping concentrations, a faulted crystal containing double Shockley faults is more stable than perfect 4H–SiC crystal at the high temperatures (>1000 °C) that the wafers are subject to during heat treatment. We have developed a model for the formation mechanism of the rhombus shaped stacking faults, and experimentally verified it by characterizing the configuration of the bounding partials of the stacking faults on both surfaces. Using high resolution transmission electron microscopy, we have verified that the enclosed stacking fault is a double Shockley type.

Abstract: In this paper we present results on the growth of low-doped thick epitaxial layers on 4° off-oriented 4H-SiC using a warm-wall multi-wafer CVD system (Aixtron VP2800WW). Statistical data on doping and thickness of 25 μm to 40 μm layer growth show results similar to standard epilayer growth (5-15 μm). Improvements in thickness and doping uniformity as well as the reduction of epitaxial defects has boosted the quality of 25 μm to 40 μm thick epilayers. Laser light scattering measurements resulted in projected device yields with median values of 83% and 96% for 5×5 mm² and 2×2 mm² die size, respectively. This corresponds to a low epitaxial defect density of < 0.75 cm^-2 in 25-40 μm thick epilayers. This paper also presents results of 60 μm to 150 μm thick epitaxial layer growth. Excellent results for doping, thickness and carrier lifetime were achieved. As an example results of a fully loaded 10×100mm run with 150 μm thick epilayers are presented. Wafer-to-wafer doping and thickness values of 3.7 % and 3.4% for sigma/mean were accomplished, respectively. Typical average lifetime values of 5 μs to 6 μs were measured on the 150 μm thick layers without post-epi treatments.

Abstract: Efforts to develop 150 mm 4H SiC bare wafer and epitaxial substrates for power electronic device applications have resulted in quality improvements, such that key metrics match or outperform 100 mm substrates. Total dislocation densities and threading screw dislocation densities measured for 150 mm wafers were ~4100 cm^-2 and ~100 cm^-2, respectively, compared with values of ~5900 cm^-2 and ~300 cm^-2 measured for 100 mm wafers. While median basal plane dislocation counts in 150 mm samples exceed those of the smaller platform, a nearly 45% reduction was realized, resulting in a median density of ~3900 cm^-2. Epilayers grown on 150 mm substrates likewise exhibit quality metrics that are comparable to 100 mm samples, with median thickness and doping sigma/mean values of 1.1% and 4.4%, respectively.

Abstract: Synchrotron white beam x-ray topography (SWBXT), synchrotron monochromatic beam x-ray topography (SMBXT), and high resolution transmission electron microscopy (HRTEM) studies have been carried out on stacking faults in PVT grown 4H-SiC crystal. Their fault vectors were determined by SWBXT to be 1/3<-1100>, 1/2<0001>, 1/6<-2203>, 1/12<4-403>, 1/12<-4403>. HRTEM studies reveal their similarity in stacking sequences as limited numbers of bilayers of 6H polytype structure. Simulation results of the two partial dislocations associated with the stacking faults in SMBXT images reveal the opposite sign nature of their Burgers vectors. A mechanism for stacking fault formation via 2D nucleation is postulated.

Abstract: Dislocation behavior during homo-epitaxy of 4H-SiC on offcut substrates by Chemical Vapor Deposition (CVD) has been studied using Synchrotron X-ray Topography and KOH etching. Studies carried out before and after epilayer growth have revealed that, in some cases, short, edge oriented segments of basal plane dislocation (BPD) inside the substrate can be drawn towards the interface producing screw oriented segments intersecting the growth surface. In other cases, BPD half-loops attached to the substrate surface are forced to glide into the epilayer producing similar screw oriented surface intersections. It is shown that the initial motion of the short edge oriented BPD segments that are drawn from the substrate into the epilayer is caused by thermal stress resulting from radial temperature gradients experienced by the wafer whilst in the epi-chamber. This same stress also causes the initial glide of the surface half-loop into the epilayer and through the advancing epilayer surface. These mobile BPD segments provide screw oriented segments that pierce the advancing epilayer surface that initially replicate as the crystal grows. Once critical thickness is reached, according to the Mathews-Blakeslee model, these screw segments glide sideways under the action of the mismatch stress leaving IDs and HLAs in their wake.