Papers by Author: Jean-Pierre Chante

Abstract: Silicon carbide devices limitations often originate from the quality of the substrate material. Therefore it is interesting to investigate devices fabricated on alternative source materials. Currently, CREE is the world market leader of SiC wafers. Nowadays, some new companies begin to propose alternative material. The European manufacturer SiCrystal furnishes now some epiwafers for the fabrication of 1,2kV devices. In this paper we present 4H-SiC 1.2 kV pin diodes with a JTE termination realized on a SiCrystal epiwafer. The devices exhibit a blocking voltage of 1.2 kV, a current density of 420 A.cm-2 and a specific differential series resistance of 4.4 m-⋅cm2. The yield of fabricated diodes with a breakdown voltage greater 600 V is superior to 75%.

Abstract: Overcoming the physical limits of silicon, silicon carbide shows a high potential for making high voltage thyristors. After a simulation based optimization of the main thyristor parameters, including JTE protection and a SiO2 layer passivation, 4H-SiC GTO thyristors were realized and characterized. Designed for a theoretical blocking capability of nearly 6 kV, the electrical characterization of all device structures revealed a maximum blocking voltage of 3.5 kV. Comparing simulation and measurement suggests that a negative oxide charge density of ~ 2×1012 cm-2 causes the decrease in electrical strength.

Abstract: Al-Si patterns were formed on n-type 4H-SiC substrate by a photolithographic process including wet Al etching and Si/SiC reactive ion etching (RIE) process. RF 1000°C annealing under C3H8 flow was performed to obtain p+ SiC layers by a Vapour-Liquid-Solid (VLS) process. This method enables to grow layers with different width (up to 800 µm) and various shapes. Nevertheless the remaining Al-based droplets on the largest patterns are indicators of crack defects, going through the p+ layer down to the substrate. SIMS analyses have shown an Al profile with high doping concentration near the surface, high N compensation and Si/C stoechiometry variation between the substrate and the VLS layer. The hydrogen profile follows the Al profile in the VLS layer with an overshoot at the VLS/substrate interface. I-V measurements performed directly on the semiconductor layers have confirmed the formed p-n junction and allowed to measure a sheet resistance of 5.5 kW/ı