Papers by Author: John W. Palmour

Abstract: The 1/f noise has been investigated for the first time at 300 and 77 K in high-quality 4H-SiC Schottky diodes. It is shown that, that at 77 K, the dependence of the spectral noise density on current, S_I(I), differs fundamentally between the cases of the current flowing through the main part of the diode area with a comparatively high barrier and the current flowing through the nanosized patches with a comparatively low barrier.

Abstract: Alkali (Rb, Cs) and alkaline earth elements (Sr, Ba) provide SiO₂/SiC interface conditions suitable for obtaining high metal-oxide-semiconductor field-effect-transistor (MOSFET) channel mobility on the 4H-SiC Si-face (0001), without the standard nitric oxide (NO) anneal. The alkali elements Rb and Cs result in field-effect mobility (μ_FE) values >25 cm²/V^.s, and the alkaline earth elements Sr and Ba resulted in higher μ_FE values of 40 and 85 cm²/V^.s, respectively. The Ba-modified MOSFETs show a slight decrease in mobility with heating to 150 °C, as expected when mobility is not interface-trap-limited, but phonon-scattering-limited. The interface state density is lower than that obtained with nitric oxide (NO) passivation. Devices with a Ba interface layer maintain stable mobility and threshold voltage under ±2 MV/cm gate bias stress at 175 °C, indicating no mobile ions.

Abstract: This study addresses the transient and steady-state performance of a >13 kV SiC ETO as a Solid-State Circuit Breaker (SSCB). The developed SiC-ETO is based on a 1 cm², 15 kV SiC p-GTO with an extremely low differential resistance. Static performance of the device, including the on-state voltage drop at different temperatures and different currents has been carried out in this paper. Furthermore, transient performance of the device, including the turn off energy of the device has been studied. Also, the superior performance of the p-type SiC-ETO has been exploited to design and implement a solid-state circuit breaker. The studies verify the superiority of the SiC p-ETO compared to other solid state devices for this application.

Abstract: Advanced high-voltage (≥10 kV) silicon carbide (SiC) devices described in this paper have the potential to significantly impact the system size, weight, high-temperature reliability, and cost of modern variable-speed medium-voltage (MV) systems such as variable speed (VSD) drives for electric motors, integration of renewable energy including energy storage, micro-grids, traction control, and compact pulsed power systems. In this paper, we review the current status of the development of 10 kV-20 kV class power devices in SiC, including MOSFETs, JBS diodes, IGBTs, GTO thyristors, and PiN diodes at Cree. Advantages and weakness of each device are discussed and compared. A strategy for high-voltage SiC power device development is proposed.

Abstract: In this work, we report our recently developed 16 kV, 1 cm², 4H-SiC PiN diode results. The SiC PiN diode was built on a 120 µm, 2×10¹⁴/cm³ doped n-type SiC drift layer with a device active area of 0.5175 cm². Forward conduction of the PiN diode was characterized at temperatures from 20°C to 200°C. At high injection-current density (J_F) of 350 ~ 400 A/cm², the differential on-resistance (R_ON,diff) of the SiC PiN diode decreased from 6.08 mΩ·cm² at 20°C to 5.12 mΩ·cm² at 200°C, resulting in a very small average temperature coefficient of –5.33 µΩ·cm²/°C, while the forward voltage drop (V_F) at 100 A/cm² reduced from 4.77 V at 20°C to 4.17 V at 200°C. This is due to an increasing high-level carrier lifetime with an increase in temperature, resulting in reduced forward voltage drop. We also observed lower R_ON,diff at higher injection-current densities, suggesting that a higher carrier lifetime is needed in this lightly doped n-type SiC thick epi-layer in order to achieve full conductivity modulation. The anode to cathode reverse blocking leakage current was measured as 0.9 µA at 16 kV at room temperature.

Abstract: In this paper, we report our recently developed 1 cm², 15 kV SiC p-GTO with an extremely low differential on-resistance (_RON,diff) of 4.08 mΩ•cm² at a high injection-current density (J_AK) of 600 ~ 710 A/cm². The 15 kV SiC p-GTO was built on a 120 μm, 2×10¹⁴/cm³ doped p-type SiC drift layer with a device active area of 0.521 cm². Forward conduction of the 15 kV SiC p-GTO was characterized at 20°C and 200°C. Over this temperature range, the R_ON,diff at J_AK of 600 ~ 710 A/cm² decreased from 4.08 mΩ•cm² at 20°C to 3.45 mΩ•cm² at J_AK of 600 ~ 680 A/cm² at 200°C. The gate to cathode blocking voltage (V_GK) was measured using a customized high-voltage test set-up. The leakage current at a V_GK of 15 kV were measured 0.25 µA and 0.41 µA at 20°C and 200°C respectively.

Abstract: We have investigated the thermal behavior of our recently developed 1200 V, 200 A 4H-SiC power DMOSFETs operating from 20°C up to 300°C. Compared to the first generation SiC DMOSFET that was commercially released early this year, this 4H-SiC power DMOSFET shows a ~ 50% reduction in the total specific on-resistance at room temperature. Temperature dependence of the key parameters of this MOSFET, such as on-resistance, threshold voltage, and the MOS channel mobility, are reported in this paper. The MOSFET showed normally-off characteristics throughout the entire experimental temperature range. Different temperature dependence of the total on-resistance in different temperature regimes has been observed.

Abstract: Initial results are presented for SiC-epitaxial growths employing a novel 6x150-mm/10x100-mm Warm-Wall Planetary Vapor-Phase Epitaxial (VPE) Reactor. The increased areal throughput offered by this reactor and 150-mm diameter wafers, is intended to reduce the cost per unit area for SiC epitaxial layers, increasing the market penetration of already successful commercial SiC Schottky and MOSFET devices [1]. Growth rates of 20 micron/hr and short <2 hr fixed-cycle times (including rapid heat-up and cool-down ramps), while maintaining desirable epitaxial layer quality were achieved. No significant change in 150 mm diameter wafer shape is observed upon epitaxial growth consistent with good-quality, low-stress substrates and low (<5°C) cross-wafer epitaxial reactor temperature variation. Specular epitaxial layer morphology was obtained, with morphological defect densities consistent with projected 5x5 mm die yields as high as 80% and surface roughness, Ra, of 0.3 nm. Intrawafer thickness uniformity is good, averaging only 1.6% and within a run wafer-to-wafer thickness variation is 2.7%. N-type background doping densities less that 1E14 cm-3 have been measured by CV. Doping uniformity and wafer-to-wafer variation currently average ~12% requiring further improvement. The first 100 m thick 150-mm diameter epitaxial growths are reported.

Abstract: We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 6.7 mm x 6.7 mm 4H-SiC N-IGBT with an active area of 0.16 cm2 showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. A 4H-SiC P-IGBT exhibited a record high blocking voltage of 15 kV, while showing a differential specific on-resistance of 24 mΩ-cm2. A comparison between P- and N- IGBTs in 4H-SiC is provided in this paper.

Abstract: We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.