Papers by Author: Josep Montserrat

Abstract: Edge termination is a critical part of a power devices. Numerous edge termination types have been developed for silicon devices. Implementation of these termination architectures are not straightforward in SiC due to physical and processing specificities: lower junction depths, higher electric field, trench depth and shaping limitations, etc. Two main families of terminations are currently used in commercial devices, pure Field Guard Rings, and JTE + Rings combination. The increasing number of trench commercial devices requires new approaches based on etched rings filled with dielectrics or polysilicon. For epitaxied bipolar devices, MESA with bevel angle termination combined with JTE based architecture are also suitable. In any case, and especially regarding avalanche capability requirements, not only the termination architecture is relevant, but also the passivation type, the channel stopper design, the 3D design. As modelling using conventional tools is not fully reliable, specific complementary characterization methods are needed. For instance, micro-OBIC can be very effective to determine the electric field distribution in the periphery of the power devices.

Abstract: This work addresses the electrical behaviour of high-voltage (HV) SiC MOSFETs, being the main motivation to check their robustness. Large area (25 mm²) devices rated for 3.3 kV applications were fabricated with a special process for the gate oxide formation. The unit cell was designed to achieve good short-circuit performance. Static and dynamic characterization is presented at room and high temperature. Output curves and 3^rd quadrant behaviour were analysed. Dynamic tests were performed at high bus voltages and high current. To check device robustness, short-circuit and power cycling’s were considered. Robustness test results put in evidence the achievement of reasonable good results obtained due to a suitable cell design.

Abstract: In this work, we have evaluated 4° off-axis Si face 4H-SiC MOSFETs channel performance along both the [11-20] (perpendicular to steps) and [1-100] (parallel to steps) orientations, to evidence possible anisotropy on Si-face due to roughness scattering effect. Improved gate oxide treatments, allowing low interface state densities and therefore high mobility values, have been used on both NO and N₂O annealed gate oxides. With these high channel mobility samples, a small anisotropy effect (up to 10%) can be observed at high electric fields. The anisotropy can be seen both at room and high temperatures. However, the optical phonon scattering is the dominant effect under these biasing conditions.

Abstract: This paper deals with investigation and fabrication of 4H-SiC MOSFETs with a high-k dielectric close to ZrSiO₄. We are looking for the optimal stochiometry in order to obtain full benefits of its large bandgap, a k value higher than that of SiO₂, thermodynamic stability on SiC, a good interface quality and process compatibility with SiC technology. Several Si/Zr ratios have been tested with the purpose of obtaining the most favorable dielectric configuration. The first test devices have been manufactured successfully with a stack gate dielectric consisting of a thin SiO₂ interlayer and a Zr_xSi_yO_z (theoretical Si/Z=0.7) layer on top.

Abstract: The fabrication of CMOS devices in SiC is important for both a higher operating temperature capability and the integration with SiC power devices. In this work, n-channel and p-channel signal MOSFETs have been successfully fabricated using a process technology fully compatible with our HV SiC VDMOS technology. A preliminary SiC CMOS inverter has been also integrated. The gate oxide configuration includes the use of Boron to improve SiO₂/SiC. Electrical characterizations have been carried out at room temperature and a summary of the results is presented. The biggest challenge is to balance the n-type and p-type MOSFETs not only in area but also in V_th value.

Abstract: SiC planar VDMOS of three voltages ratings (1.7kV, 3.3kV and 4.5kV) have been fabricated using a Boron diffusion process into the thermal gate oxide for improving the SiO₂/SiC interface quality. Experimental results show a remarkable increase of the effective channel mobility which increases the device current capability, especially at room temperatures. At high temperatures, the impact of the Boron treatment is lower since the major contribution of the drift layer to the on-resistance. In addition, the intrinsic body diode characteristics approximate to that of an ideal PiN diode, and the blocking capability is not compromised by the use of Boron for the gate oxide formation.

Abstract: A new oxide configuration for the development of high mobility 4H-SiC lateral MOSFETs is proposed in this work. The oxide is composed by a rapid thermal oxidation (RTO) in N₂O environment, a Boron diffusion into the SiO₂ and a PECVD TEOS deposited oxide, in order to improve the interface quality. The obtained MOSFETs show very high peak field effect mobilities ranging from 80 up to more than 170 cm²V^-1s^-1 in MOSFETs with higher channel length than the tested transistors. The physical (SIMS) and electrical analysis of the oxide and SiC surface reveals that the Boron has not diffused into the SiC. This is most probably due to the high concentration of Nitrogen at the interface generated during the N₂O oxidation.

Abstract: The electrical behaviour of irradiated and post-irradiation annealed nMOSFETs with an implanted p-type body and having a N₂O oxynitrided gate oxide is analysed in this work. This study reveals the existence of a “threshold fluence” which might change the predominant SiO₂/SiC interface charge trapping type from donors to acceptors at a given energy. The irradiation fluence and energy limit that guaranty a normal or improved operation of the MOSFETs are also given.

Abstract: This work reports experimental results on surge current capability of press-pack SiC diodes: Schottky, JBS and PIN. Our investigation showed a strong improvement of electro-thermal performances of the surge current capability for the 5.5 kV JBS diodes by using press-pack encapsulation. The surge current failure analysis for the press-pack SiC diodes is described together with a simplified unidimensional model for the temperature evaluation at the failure point.

Abstract: In this work, a charge pumping characterization has been carried out on 4H-SiC nMOSFETs built with different SiC doping processes. Because charge pumping (CP) measurements on SiC are complex to implement, three different CP methods have been used for D_it characterization. The impact of geometrical and electrical parameters on each method is studied. Finally, it is detailed the full measurement flow chosen for a deeper and more accurate understanding of D_it electrical characterization.