Papers by Author: Kenji Fukuda

Abstract: This study developed two types full SiC half bridge power module, which consist of IEMOS (Implantation Epitaxial MOSFET / Planer structure) or VMOS (V-groove trench MOSFET / Trench structure). The switching loss and conduction loss of the power module are evaluated in H bridge circuit. The VMOS module experimentally shows less loss than IEMOS module.

Abstract: This paper presents the experimental results of static and dynamic characteristics of the newly developed 14 kV 4H-SiC high-speed drift step recovery diode (DSRD) for pulse power applications for the first time. The feature of the diode structure is to be designed based upon the p+/p-/n+ structure and is to make an additional extremely low doping and thin n-drift layer between the p-drift layer and n+ substrate. This device successfully exhibits higher breakdown voltage of 14kV and high-speed voltage pulse in a range of a few nanoseconds, simultaneously.

Abstract: This paper develops 1200V, 50A full SiC half bridge power module, which embeds C snubber and gate resistors. Embedded C snubber suppresses surge voltage in fast switching operation, and gate resistors avoid gate oscillation of parallel connected SiC MOSFET in the module. 1MHz switching operation of developed module with 600V DC-link voltage is experimentally confirmed.

Abstract: We investigated the relationship between ion implantation-induced defects and electrical characteristics, especially focusing on the leak failure rate in SiC IEMOSs and PN diodes. It was found that dislocation exists in each leakage point by analyzing identical leak-failed IEMOS by emission microscopy and refraction X-ray topography. The leak failure rate of the PN diodes and IEMOS was improved with an increase in the ion implantation temperature under the implantation and annealing conditions used in this experiment. It is considered that ion implantation-induced defects lead to an increase in leak failure rates, and also enable a decrease in leak failure rates by raising the implantation temperature up to 600 deg.C.

Abstract: The static and dynamic characteristics of 13-kV class 4H-SiC junction barrier Schottky (JBS) diodes with a three-zone junction termination extension (JTE) are presented. Using an anisotropy breakdown model, technology computer-aided design simulation of devices with a three-zone JTE agrees well with the obtained experimental results, correctly predicting a sharp drop in blocking voltage at high JTE acceptor concentrations. The forward voltage of the JBS diode at 75°C and a forward current of 500 mA is reduced to approximately one-ninth by that of 13 series-connected 1000-V Si PiN diodes. This suggests that conduction losses of traditional high-voltage circuits which conventionally use series-connected devices can be drastically reduced by replacing the series-connected devices with a single 13-kV class SiC JBS diode. Moreover, the reverse recovery current waveform of the 13-kV class SiC JBS diode shows that these diodes have lower reverse recovery losses than a 13-kV SiC PiN diode.

Abstract: Wet and N₂O oxidized SiO₂/SiC for C-face substrates were comprehensively investigated to clarify the origin of oxide defects which affect channel mobility and threshold voltage stability by using leakage-current analysis. The estimated defects are identified by cathode luminescence, X-ray photoelectron spectroscopy, and high-resolution Rutherford backscattering spectroscopy. The origin of the observed oxide defects might be complex defect of O vacancy defects and/or C related defects including N.

Abstract: We have systematically investigated the trench properties of 4H-SiC for p-type channel doping level formed by epitaxial growth, crystallographic plane, and MOS interface treatment. Our results show that the channel mobilities on the (1-100), (11-20), (-1100), and (-1-120) planes gradually decreased in the range from 1 × 10¹⁶ to 1 × 10¹⁷ cm^-3 as the epitaxial channel concentration increased. An inevitable tradeoff existed between channel mobility (field-effect mobility, µ_FE) and threshold voltage (V_th) in trench MOSFETs. Furthermore, the maximum µ_FE at a channel concentration of 1 × 10¹⁷ cm^-3 was 95 cm²·V^-1·s^-1 on the (11-20) plane with wet + hydrogen (H₂) annealing, 83 cm²·V^-1·s^-1 on the (1-100) plane with wet + H₂ annealing and 57 cm²·V^-1·s^-1 on the (1-100) plane with nitric oxide annealing.

Abstract: In this paper, newly developed 3300V-class IEMOSFETs were presented. By means of the optimization of current spreading layers (CSLs), we could achieve low specific on-resistance (R_ONA) of 11.6mΩcm², while maintaining high blocking voltage (BV_DSS) of 3978V. The R_ONA analysis revealed drastic reduction of JFET resistance compared to a MOSFET without a CSL. High ruggedness with the avalanche withstanding energy of 4.6J/cm² was achieved by the optimal device design of the edge termination. We could also confirm favorable characteristics of R_ONA, BV_DSS and threshold voltage (V_TH) at high temperatures up to 200^○C, and the fast switching behavior.

Abstract: We investigated the effect of the basal plane dislocation (BPD) density in 4H-silicon carbide (SiC) substrates on the forward voltage (V_sd) degradation of body-diodes. Using reflection X-ray topography, the BPD density was automatically estimated from the substrates prior to fabrication of metal–oxide–semiconductor field-effect transistors (MOSFETs). A strong positive correlation was found between the V_sd shift, which was calculated from the difference before and after forward bias stress at 160 A/cm² for ~500 hours, and the BPD density of the substrate. We show that it is possible to predict V_sd shifts from the BPD densities of SiC substrates prior to the fabrication of MOSFETs. In addition, we examined the origin of stacking faults (SFs) as a result of the application of forward bias stress. We presume that SFs are formed by BPDs converted to threading edge dislocations at the epi/sub interface, as well as by BPDs penetrating into the epitaxial layer.

Abstract: In this study, 4H–SiC inversion layers were experimentally evaluated by Hall and split C–V measurements, and scattering mechanisms related to gate oxide nitridation were analyzed. Three typical samples with different crystal plane directions and gate oxidation conditions were prepared, and their total trap density and Hall mobility were compared. Based on the temperature dependence of the Hall mobility, we found that scattering mechanisms differed for each sample. The sample C-face oxynitride which had a high nitrogen density at the metal–oxide–semiconductor (MOS) interface, showed a similar temperature dependency to that of ionized impurity scattering. This result suggests that high-density nitrogen acts as donors that supply free carriers and cause ionized impurity scattering, just like in a bulk crystal. In addition, the sample C-face wet has lowest influence of the Coulomb scattering because of the lowest temperature dependence of Hall mobility and the lowest total trap density.