Papers by Author: Konstantinos Zekentes

Abstract: 4H Silicon Carbide multichannel neural interface devices using NPN junctions for channel isolation were fabricated using four different doping structures. Two devices used thicker, lower-doped epitaxial layers, one used thin, highly-doped implanted layers implanted into a N epilayer, and one used thin-highly-doped implanted layers into an N substrate. The devices were characterized in terms of resistance, charge delivery, leakage current through the substrate, and crosstalk between channels. The thickest, lower-doped epitaxial layers performed best, resulting in great isolation and good performance. While the implanted layers showed high charge delivery, their resistance is reduced due to the thin layers and the isolation is particularly poor.

Abstract: This work aims to optimize Plasma-Enhanced Chemical Vapour Deposition (PECVD) amorphous hydrogenated silicon carbide (a-SiC:H) as a conformal passivation layer for invasive microelectrode array (MEA) neural interface applications. By carefully tuning the PECVD deposition parameters, the composition, structure, electrical, and mechanical properties of the films can be optimized for high resistivity, low stress, and great resistance to chemical attack. This optimization will eventually allow a-SiC:H to be used as an ideal insulation, passivation and protection layer for thin and biocompatible all-SiC neural interfaces.

Abstract: In this paper, a suitable process technology is employed to fabricate a new open gate silicon carbide-based junction field-effect transistor (OG-4H-SiC-JFET) intended to be used for all types of biochemical sensing applications. The main focus is dedicated to the fabrication steps and specifically the plasma etching of the SiC as it is the key step to pattern the device components. All necessary I-V characteristics (I_DS-V_DS and I_DS-V_GS) have been derived and show acceptable electrical performance. Furthermore, the electrical characteristics of the OG-4H-SiC JFET were simulated using 3D Silvaco ATLAS and are in line with the experimental electrical characteristics. The efficacity and simplicity of the process described in this paper is the first step for future development of biochemical sensors based on SiC-FETs.

Abstract: A SiCNWFET device serving as a biosensor was designed and simulated using Silvaco ATLAS device simulation software. The performance of the designed device in charges sensing was investigated. The device shows the ability to recognize different interface charge values ranging from-1.10E11 to-5.10E12 cm^-2 applied on the surface of the silicon carbide nanowire channel to simulate target charge biomolecules that bound to the biosensor. A significant change in the output current is observed due to the presence of different values of fixed interface charge densities. An optimum, according to the TCAD simulation, the 4H-SiC epitaxial structure has been grown. The designed device was fully fabricated on this structure and it exhibited acceptable electrical characteristics.

Abstract: High temperatures and other harsh environments are domains of predilection for Junction FETs, particularly when wide band-gap semiconductors such as SiC or GaN are used. The present work describes the new compact model of double gate (DG) JFETs which is compared to TCAD simulations of SiC and GaN JFETs over a wide temperature range up to 500oC. The compact model is shown to be predictive of device behavior, for static (current-voltage) as well as dynamic (capacitance-voltage) behavior of long-channel DG JFETs.

Abstract: Secondary electron imaging of SiC epi-structures is commonly used as it allows doping topography i.e. the knowledge of the spatial extension of differently doped layers. Determination of the doping level of the layers was not possible until now. The present work presents how to use this technique for 4H-SiC p-type doping determination. This is indeed, possible for specific experimental data analysis and for doping levels higher than 10¹⁷cm^-3.

Abstract: This paper presents and discusses the depletion mechanisms that dominate in a TSI-VJFET under different bias conditions as expressed by the gate-source (C_GS) and gate-drain (C_GD) capacitances. It is shown that at pinch off the dominant capacitance is the drift capacitance and that in conduction the drain source voltage plays a significant role in channel’s formation. Furthermore a semi empirical capacitance model is introduced. C_GS and C_GD are modeled below and above threshold voltage by considering parallel plate capacitors with different plate configuration in te two cases. Then, the derived expressions are unified using a transition function that preserves the continuity of the model. The model was adjusted and fitted adequately to measured CV data from fabricated TSI-VJFET.

Abstract: Different methods for cross-section characterization of SiC Trenched-singly-implanted vertical junction field effect transistors (TSI-VJFETs) are presented with the purpose to determine the epitaxial structure in terms of doping topography.

Abstract: The threshold voltage of SiC JFETs has been determined from transfer characteristics by employing methods commonly used in the case of MOSFETs. The extracted values have been compared with the value determined from the fitting of experimental transfer characteristics with the Schockley model equation. Moreover, the variation of the extracted threshold voltage values with respect to channel width has been employed to determine the channel concentration without taking into account the V_bi value.

Abstract: Internal device capacitances in 4H-SiC based devices play an important role in determining their performances. In the present work, an analysis of the capacitance measurements in 4H-SiC trenched and single-implanted (TSI) gate vertical JFET TSI-VJFETs has been undertaken. Physical parameters such as threshold voltage and the related to its value effective channel length as well as channel layer and drift layer doping profiles have been extracted. The measured internal capacitances have been modeled by various models based on device physics.