Papers by Author: Kurt Wostyn

Abstract: The use of SiGe substrate as a semiconductor material is increasing because of its unique properties. In order to manufacture high-performance devices, it is necessary to develop SiGe selective etching technology. In this study, SiGe epi and oxide substrates with varying germanium percentages (15, 25, and 40 %) were used for the investigation of the selective etching process. As the etchant, APM (1:4:20) solutions were used, and added HF and HCl to confirm the pH effect. The evaluation was conducted while adjusting the pH level. In the case of the SiGe epi substrate, the etching rate was very low at high pH, but the etching rate rapidly increased at a specific pH. And then, the etch rate gradually decreased. On the other hand, the etch rates of the oxide substrate rapidly increased as the pH decreased. To explain the etch rate behavior due to the difference in Ge content and type of substrates, the surface chemistry was measured, and the speciation of the solution was analyzed.

Abstract: The steam oxidation of SiGe shows a transition from Si-like to Ge-like oxidation behavior depending on Ge concentration and oxidation temperature. Ge-like oxidation is described by the generation of oxygen vacancies (VO) at the interface between the oxide and SiGe virtual substrate. [1] Due to the different oxidation behavior, the presence of a Ge-oxide-free interfacial layer (IL) can suppress SiGe oxidation. [2] Here we show how a passivating interfacial layer can be grown using low-pressure oxidation and highlight the importance of SiGe surface preparation prior to low-pressure oxidation.

Abstract: Gate All-Around (GAA) is considered a key design feature for future CMOS technology. SiGe vs. Si selective etch is required for Si nanowire formation in GAA. It is confirmed the selective SiGe removal with commodity chemical (mixtures of hydrofluoric acid (HF), hydrogen peroxide (H2O2) and acetic acid (CH3COOH, HAc)), however the thick oxidized layer on Si NW was observed after commodity chemical process, which is indicated the significant Si NW loss. On the other hand, the formulated mixture ACT® SG-101, which is focusing on SiGe oxidizer, chemical pH, solvent polarity & corrosion inhibitor for chemical concept, was performed higher selectivity and lower Si loss than commodity chemical. The formulated mixture has also been used to form an inner spacer for cavity etch scheme and confirmed uniform cavity etch and inner spacer filling on topological test structure.

Abstract: For horizontally stacked nanowires or-sheets to compete with finFET, the development of a robust inner spacer module is essential. These inner spacers are required to reduce the parasitic capacitance due to the overlap between the source/drain and gate regions. Here we propose an inner spacer integration scheme for Si gate-all-around (GAA) taking advantage of the selective oxidation and oxide removal of SiGe versus Si. Compared to thermal oxide, we found a very high SiGe-oxide etch rate in aqueous HF solutions. When using an NH₃/NF₃ remote plasma, a reduction in etch rate was found for SiGe-oxide versus thermal oxide. We show Si_0.75Ge_0.25-oxide meets inner spacer requirements for leakage current and electrical breakdown field and finally demonstrate the proposed inner spacer integration scheme using a fin-shaped SiGe/Si multilayer topological-test-structure.

Abstract: A selective wet etching process for fabricating SiGe and Ge nanowires for gate all around transistors is introduced in this paper. Two formulated proprietary chemical mixtures with highly selective etching properties (Si vs. SiGe and SiGe vs. Ge) can effectively dissolve the sacrificial layers with minimal damage to the interstitial nanowire materials. The Auger Electron Spectroscopy (AES) surface characterization indicates that no chemical contamination is left after the wet etching process.

Abstract: For the Ge nanowire formation in a gate-all-around (GAA) integration scheme, a selective etch of Si_0.5Ge_0.5 or Si_0.3Ge_0.7 selective to Ge is considered. Two wet process approaches were evaluated: a boiling TMAH as a commodity chemistry is compared with a formulated chemistry using a multi-stack SiGe/Ge layer as a test vehicle. The boiling TMAH exhibits an anisotropic etch of the SiGe whereas the formulated semi-aqueous chemistry removes the sacrificial SiGe by an isotropic etch which makes the process suitable for a Ge nanowire release process.

Abstract: Ultrapure water contains dilute hydrogen peroxide as an impurity. In order to clarify an impact of the dilute hydrogen peroxide on cleaning processes, a SiGe epitaxial layer was deposited on a Si(100) wafer which surface was treated by HF last process with hydrogen peroxide contained UPW or hydrogen peroxide removed UPW. The defect in the SiGe epitaxial layer was reduced when the hydrogen peroxide removed UPW was used.

Abstract: Epitaxial growth requires a clean starting surface for the growth of a high-quality crystalline layer. For epitaxy on Si, an HF-last wet clean followed by an in-situ high-temperature hydrogen bake is the reference pre-epi clean sequence to obtain an oxygen-free surface [1, 2]. The temperature required to remove all residual oxygen also makes the surface atoms mobile, resulting in reflow. The high temperatures used during the H₂-bake can also result in intolerable doping profile changes. A lower temperature pre-epi clean sequence is required to avoid this reflow, especially when moving away from Si. In addition the high temperatures needed during a H₂-bake would result in the relaxation of high mobility channels, e.g. strained Si_1-xGe_x or III-V materials [3]. Several low temperatures pre-epi cleaning solutions have been proposed in the past, e.g. GeH₄-assisted H₂-bake [4] or more recently, a GeH₄-assisted HCl clean [5]. In this study we looked at the interaction between HF-last wet clean and the in-situ GeH₄-assisted HCl clean prior to Si_0.8Ge_0.2-on-Si epitaxy.

Abstract: The cumulative installed solar power generation has been rising exponentially over the past decade. This has lead to a concomitant rise in production capabilities, leading eventually to excess production capabilities and rapid price declines per unit. In order to compete with the standard electricity generation the cost of solar panel production and installation needs to decrease even further. At the same time the solar panel and cell makers need to be able to keep a healthy margin. A crucial element in this exercise is a close control on the Cost of Ownership (CoO) of a solar cell / panel fabrication site.

Abstract: Thermal atomic layer deposition (ALD) of Al2O3 provides an adequate level of surface passivation for both p-type and n-type Si solar cells. To obtain the most qualitative and uniform surface passivation advanced cleaning development is required. The studied pre-deposition treatments include an HF (Si-H) or oxidizing (Si-OH) last step and finish with simple hot-air drying or more sophisticated Marangoni drying. To examine the quality and uniformity of surface passivation - after cleaning and Al2O3 deposition - carrier density imaging (CDI) and quasi-steady-state photo-conductance (QSSPC) are applied. A hydrophilic surface clean that leads to improved surface passivation level is found. Si-H starting surfaces lead to equivalent passivation quality but worse passivation uniformity. The hydrophilic surface clean is preferred because it is thermodynamically stable, enables higher and more uniform ALD growth and consequently exhibits better surface passivation uniformity.