Papers by Author: Lucile Broussous

Abstract: A post-etch residue cleaning formulation, based on balancing the aggressiveness of hydrofluoric acid with its well-known residue removal properties is introduced. In a series of investigations originally motivated by the cleaning challenge provided by high-k dielectric-based residues, a formulation platform is developed that successfully cleans residues resulting from the plasma patterning of tantalum oxide and similar materials while maintaining metal and dielectric compatibility. It is further shown that the fundamental advantages of this solution can be extended to the cleaning of other, more traditional post-etch residues, with no sacrifice in compatibility, as demonstrated by measurements on blanket films and through SEM data.

Abstract: For integrated circuit fabrication on 300 mm wafers, copper interconnections cleaning is generally done with single wafer tools. In this study, we focused on the cleaning of aluminum interconnections, on single wafer tool, with a cheap and easy to use chemistry. Aluminum compatibility with diluted HF solutions was first evaluated, then short and efficient cleaning processes were developped for two kind of applications : cleaning after aluminum line etching and cleaning after final dielectric etching over the aluminum pad. It was demonstrated that cleaning efficiency was poor for the shorter process time (20 s), but improved with process time increase, highlighting a lift-off mechanism for polymers removal. Best process was achieved with 40 s of HF 0.2%, that offers a good compromise between polymer removal and lateral recess of the aluminum.

Abstract: For 28 nm and beyond, severe specifications in terms of dimensions and materials integrity still drive further cleaning process improvements. As the global “HF budget” drastically decreases with interconnections dimensions, HF solution dilution and process time both decreased stepwise. However, very short recipes with process time shorter than 15s start to suffer from lack of robustness, in particular for the monitoring of inline parameters such as flow-rates and temperature. In this paper, we highlighted that a first matching of silicon oxide consumption was usefull to select temperature and concentration range for the diluted HF solution. High dilution ratio, and “room temperature” (20 °C) were then selected. Variations in cleaning efficiency were analyzed as regard with electrical defects density at three metals levels, then the use of 0.025 %wt. HF, 20 °C, 40 s. was pointed out as the more promising solution for process of record replacement. Process robustness, i.e. inline monitoring data collection and uniformity on wafer should thus be improved thanks to this longer process time and a lower process temperature.

Abstract: Wetting efficiency of microstructures or nanostructures patterned on Si wafers is a real concern in integrated circuits manufacturing. We present here a high-frequency acoustic method which enables the local determination of the wetting state of a liquid on real DTI and TSV structures. Partial wetting states for non-hydrophobic surfaces or low surface tension liquids are detectable with this method. Filling time of TSV structures has also been measured.

Abstract: Wet processing with low oxygen content may provides some advantages, however, full control to avoid oxygen uptake during wafer processing remains a challenge for short process industrialization on single wafer tool. Inline oxygen concentration monitoring was used for process optimization. Then, cobalt etch in diluted HF solutions was evaluated depending on the recorded oxygen concentration and hardware available options for atmosphere control in the process chamber.

Abstract: Porous low-k materials used as insulator for interconnection levels in CMOS devices, are easily damaged during the patterning processes. Pore size characterization after material damage is challenging due to the chemical modification induced by the applied process. Numerical simulation of solvent adsorption on silica and functionalized silica surfaces was used to improve material pore size determination by ellipso-porosimetry, taking into account the modifications of surface/solvent interactions.

Abstract: TiN Hard Mask (TiN-HM) integration scheme has been widely used for BEOL patterning in order to avoid ultra low-k (ULK) damage during plasma-ash process [1]. As the technology node advances, new integration schemes have to be used for the patterning of features below 80 nm pitch with 193 nm immersion lithography. In particular, thicker TiN-HM is necessary in order to ensure Self-Aligned-Via (SAV) integration which resolves via-metal short yield and TDDB issues caused by Litho-Etch-Litho-Etch (LELE) misalignment [2, 3]. The Cu filling process is significantly more difficult if the thick TiN is not removed because of the high aspect ratio of the structures. Moreover, with the use of TiN hard mask, a time-dependent crystal growth (TiCOF) residue may forms between line etch and metal deposition [4, 5], also hindering copper filling. Post-Etch-Treatment after line etching is one solution to the problem but N₂ plasma is not efficient enough to suppress the residue completely [6], and the CH₄ treatment proposed in [5] may be difficult to implement for 14 nm node, thus an efficient wet strip and clean provides a better solution.

Abstract: Titanium Nitride metal hard mask was first introduced for BEOL patterning at 65 nm [1] and 45 nm nodes [2]. Indeed, in this “Trench First Hard Mask” (TFHM) backend architecture, the dual hard mask stack (SiO₂ & TiN) allows a minimized exposure of ULK materials to damaging plasma chemistries, both for line/via etch sequence, and lithography reworks operations. This integration scheme was successfully used for a BEOL pitch down to 90 nm for the 28 nm node, however, for the 14 nm technology node, 64 nm BEOL minimum pitch is required for the first metal levels. Because it is unable to resolve features below 80 nm pitch in a single exposure, conventional 193 nm immersion lithography must be associated with dual patterning schemes, so called Lithography-Etch-Lithography-Etch (LELE) patterning [3] for line levels and self-aligned via (SAV) process [4] for via patterning. In both cases, 2 lithography/etch/clean sequences are necessary to obtain one desired pattern, and associated reworks also become more challenging since first pattern is exposed to resist removal processes (plasma + wet clean). The reference wet cleans that were developed for 65 to 28 nm TiN hardmask patterning, utilizes commonly used chemistry for BEOL post-etch cleans, i.e. diluted hydrofluoric acid (dHF) followed by deionized water Nanospray (DIWNS) on 300 mm single wafer tool.

Abstract: For the 32nm logic technology and beyond, more stringent specifications in terms of dimensions and materials integrity continue to drive the cleaning process improvements. In this paper, post-etch wet cleaning was optimized in order to address CD loss issues and metal hard mask cleaning improvement in a Trench First Hard Mask (TFHM) backend architecture. Based on materials compatibility tests and electrical results, this wet clean process should also be fully compatible with a Via First Trench Last (VFTL) architecture.

Abstract: The integration of CoWP and CoWB self-aligned barriers (SAB) for 32 nm technology nodes allows improving copper interconnections reliability [1, 3]. However the introduction of such materials in copper interconnection levels drives new challenges for plasma dry etch and wet clean processes. Indeed, during the post-via-etch cleaning step, cobalt and copper can be altered by corrosion. Moreover, a galvanic coupling between cobalt, the major component of SAB, and copper can thermodynamically occur. In this way, the cleaning solution acts as ionic medium providing a contact between the two metals. Thus, both metals polarize to a mixed potential comprised between the individual open circuit potentials (OCP) of cobalt and copper. As a result, the less noble metal can suffer from accelerated corrosion, and the more noble metal corrodes with slower rate. According to thermodynamic aspects, cobalt in contact with copper is the less noble metal. Consequently, Co is susceptible to undergo galvanic corrosion which may enhance the dissolution of the SAB.