Papers by Author: Markus Andreas Schubert

Abstract: The results of this work have shown that for microelectronic applications, gettering at dislocations is less important and oxygen precipitates are the main getter sink for Cu. Sufficient gettering of Cu in samples contaminated with low Cu concentration requires a higher density and larger oxygen precipitates compared to samples contaminated with high Cu concentration. It is demonstrated that the getter efficiency depends on the contamination level of the samples and getter test with low contamination level must be applied for microelectronic applications. Furthermore, a getter test for 3D chip stack technologies was developed. It was shown that although the wafers are thinned to a thickness of 50 μm their getter efficiency seems to be higher than for wafers of the original thickness. This is assumed to be due to the higher Cu concentration in the thinner wafers which can be gettered easier. It is also demonstrated that BMDs can getter Cu impurities even if the temperature does not exceed 300 °C. The getter efficiency tends to be higher if the samples are stored under day light and not in the dark.

Abstract: The integration of germanium (Ge) into silicon-based microelectronics technologies is currently attracting increasing interest and research effort. One way to realize this without threading and misfit dislocations is the so-called nanoheteroepitaxy approach. We demonstrate that a modified Si nanostructure approach with nanopillars or bars separated by TEOS SiO₂ can be used successfully to deposit SiGe dots and lines free of misfit dislocations. It was found that strain relaxation in the pseudomorphically grown SiGe happens fully elastically. These studies are important for the understanding of the behavior of nanostructured Si for the final goal of Ge integration via SiGe buffer.

Abstract: Selective epitaxial growth of germanium (Ge) on nano-structured Si(001) wafers is studied to evaluate the applicability of the nano-heteroepitaxy (NHE) approach on Ge-Si system. Based on a gate spacer technology established in advanced silicon microelectronics periodic arrays of nano-scaled Si islands are prepared, where Ge is deposited on top by reduced pressure CVD. The spacing of these structures is 360 nm. The structural perfection of the deposited Ge is investigated by transmission electron microscopy and X-ray diffraction. It is found that SiO₂ used as masking material is responsible for the suppression of the desired strain partitioning effect according to NHE. Even for 10 nm oxide thickness, the lattice of Ge layers deposited on Si nano-islands relaxes completely by generation of misfit dislocations at the interface. The occurrence of additional structural defects like stacking faults and micro twins can be controlled by suited growth conditions.