Papers by Author: Masayuki Imaizumi

Abstract: External Schottky barrier diodes (SBD) are generally used to suppress the conduction of the body diode of MOSFET. A large external SBD is required for a high voltage module because of its high specific resistance, while the forward voltage of SBD should be kept smaller than the built-in potential of the body diode. Embedding SBD into MOSFET with short cycle length increases maximum source-drain voltage where body diode remains inactive, resulting in high current density of SBD current. We propose a MOSFET structure where an SBD is embedded into each unit cell and an additional doping is applied, which allows high current density in reverse operation without any activation of body diode. The proposed MOSFET was successfully fabricated and much higher reverse current density was demonstrated compared to the external SBD. We can expect to reduce total chip size of high voltage modules using the proposed MOSFET embedding SBD.

Abstract: High threshold voltage low loss 600 V 4H-SiC MOSFETs have been fabricated successfully using a re-oxidation technique for gate oxides and an n-type doping in the Junction Field Effect Transistor region of the MOSFET with shrunk MOS cells. The MOSFET has exhibited a high threshold voltage of more than 4 V and a low specific on resistance of 5.2 mΩ·cm² at 25 °C. The MOSFET has also exhibited a sufficient blocking characteristic at V_G of 0 V at 150 °C. High speed switching with low switching losses has been demonstrated successfully using the MOSFET at 150 °C.

Abstract: This paper investigates thereduction of parasitic resistance (JFET resistance) betweenthe p-well and the grounded p-type gate-oxide protection layer (BPW)of a trench-gate SiC-MOSFET. Forming a deeptrench is a way to reducethe JFET resistance, but this consequently leads to high electric field at thebottom oxide. In order to improve the trade-off between the specific on-resistance (R_on,sp) and the maximum bottom oxide electric field (E_ox), wenewly developed a trench-gate SiC-MOSFET with an n-type region, named DepletionStopper (DS), formed under the entire p-welllayer. As aresult of fabrication, R_on,sp of the trench-gate SiC-MOSFET with DS is70 % lower than that without DS at a trench depth (d_t) of about 1.5 mm. The d_tof the trench-gate SiC-MOSFET with DS can be designed 25 % shallower than thatwithout DS at a R_on,sp of about 3.0 mWcm².Therefore, it can reduce the JFET resistance and allow to shrinkthe trench depth. Optimizing the parametersof DS, the structure having DS is an effective means of reducing the JFETresistance, while reducing E_ox by minimizing the depth of the trench.

Abstract: The reduction of the growth pressure was demonstrated to have the same effect as the addition of chloride-containing gas on preventing the Si nucleation and the epitaxy with high growth rate (>50 μm/h) was achieved by using the decreasing pressure condition in a horizontal CVD reactor without chloride-containing gas. The quality of a 30-μm-thick epilayer grown with 40 μm/h was also investigated. Downfall and triangle defect density in the layer was as low as 0.16 /cm², indicating that a high quality epitaxial wafer can be easily obtained under the condition with high throughput in the sinple CVD system.

Abstract: Edge termination guaranteeing high breakdown voltage and robustness in its fabrication are required in SiC power devices. We newly employed the VLD edge termination for 3.3 kV-rated SiC SBDs, which was formed by Al ion implantation using a resist mask having a varying thickness. The breakdown voltage is recorded to be over 96% of the parallel-plane breakdown voltage, and the reverse bias characteristics are well accorded with the result of TCAD simulation.

Abstract: SiC epitaxial layer with low basal plane dislocation (BPD) density of 0.2/cm² was successfully grown under higher C/Si ratio, which is found on the investigation about growth conditions. In order to study conversion mechanism of BPDs to threading edge dislocations (TEDs), angles between directions of BPD lines on a substrate and that of moving edges of steps ([11-2) during growth were examined. Consequently, it was revealed that almost 98% of BPDs are converted to TEDs for the case of the absolute angles above 45°. This high conversion ratio is considered to be induced by enhanced lateral growth under the higher C/Si ratio condition.

Abstract: TDDB for n-type 4H-SiC MOS capacitors depleted by DC bias (named as depletion-mode TDDB) has been investigated. The lifetime distribution can apparently be classified into two groups: shorter and longer t_BD. Breakdown for the shorter t_BD occurs at a point close to a threading dislocation. In contrast, the capacitors possessing longer t_BD include no dislocation. An increase in the stress temperature and/or E_OX leads to a decrease in t_BD, indicating that the breakdown is caused by gate-oxide degradation. On the other hand, the t_BD distributions acquired by accumulation-mode TDDB are relatively even, and the breakdown point is independent of dislocations. We presume that holes excited in the SiC layer by hot electrons play an important role at a threading dislocation for depletion-mode TDDB.

Abstract: Ensuring gate oxide reliability and low switching loss is required for a trench gate SiC-MOSFET. We developed a trench gate SiC-MOSFET with a p-type region, named Bottom P-Well (BPW), formed at the bottom of the trench gate for bottom oxide protection. We can see an effective reduction in the maximum bottom oxide electric field (E_ox) and a significant improvement in dynamic characteristics with a grounded BPW, whose dV/dt is 76 % larger than that with a floating BPW due to reduction in gate-drain capacitance (C_gd). The grounded BPW is found to be an effective means of both suppressing E_ox and reducing switching loss.

Abstract: A new growth method for considerably suppressing generation of carrot and triangle defects is presented. Based on the investigation for the surfaces before and after the epitaxial growth, it becomes clear that those defects were results from micrometer-scale SiC particles. For removing the particles, pre-flow of H₂ at high temperature before the growth was very effective. The density of those defects strongly depends on the condition of the pre-flow and especially decreased at Tp=1575°C and tp=180 sec.

Abstract: We found that threshold voltage (V_th) of a 4H-SiC MOSFET increases drastically by performing low temperature wet oxidation after nitridation in a gate oxide process. The increment of V_th depends on the wet oxidation conditions. Wet oxidation increases the interface trap density (D_it) at deep level of SiC bandgap and decreases positive charge density inside the gate oxide layer. The amount change of the interface traps and the positive charges in the gate oxide makes V_th higher without a decrease in the channel mobility. We improved the trade-off between V_th and effective carrier mobility (μ_eff) in the MOSFET channel, and realized a low specific on-resistance (R_on,sp) SiC-MOSFET with V_th over 5 V by using the newly developed process.