Papers by Author: Mietek Bakowski

Abstract: 1.2 kV SiC buried grid junction barrier Schottky (BG-JBS) diodes are demonstrated. The design considerations for high temperature applications are investigated. The design is optimized in terms of doping concentration and thickness of the epilayers, as well as grid size and spacing dimensions, in order to obtain low on-resistance and reasonable leakage current even at high temperatures. The device behavior at temperatures ranging from 25 to 225^ºC is analyzed and measured on wafer level. At 100 A/cm² a forward voltage drop of 2 V at 25^ºC and 3 V at 225^ºC is achieved. At reverse voltage of 1 kV, a leakage current density below 0.1 µA/cm² and below 0.1 mA/cm² is measured at 25 and 225^ºC, respectively. This proves the effective shielding effect of the BG-JBS design and provides benefits in high voltage applications, particularly for high temperature operation.

Abstract: The temperature evolution during a short-circuit in the die of three different Silicon Carbide1200-V power devices is presented. A transient thermal simulation was performed based on the reconstructedstructure of commercially available devices. The location of the hottest point in the device iscompared. Finally, the analysis supports the necessity to turn off short-circuit events rapidly in orderto protect the device after a fault.

Abstract: RF power amplifier demonstrators containing each one GaN-on-SiC, HEMT, CHZ015A-QEG, from UMS in SMD quad-flat no-leads package (QFN) were subjected to thermal cycles (TC) and power cycles (PC) followed by electrical, thermal and structural evaluation. Two types of solders i.e. Sn₆₃Pb₃₆Ag₂ and lead-free SnAgCu (SAC305) and two types of TIM materials (NanoTIM and Tgon^TM 805) for PCB attachment to liquid cold plate were tested for thermo-mechanical reliability. Changes in electrical performance of the devices namely reduction of the current saturation value, threshold voltage shift, increase of the leakage current and degradation of the HF performance were observed as a result of an accumulated current stress during PC. No significant changes in the investigated solder or TIM materials were observed.

Abstract: – Thermal contact resistances between a silver metallized SiC chip and a Molybdenum substrate and between the Molybdenum substrate and bulk Copper were measured in a heat transfer experiment. An experimental method to separate thermal contact resistances in a multilayer heat transfer path was used to extract the layer-specific contact resistances. The experimental results were compared with analytical calculations and also with 3-D computational fluid dynamics (CFD) simulation results. The results show significant pressure dependence of the thermal contact resistance and the results show higher thermal contact resistance per unit area between the bulk SiC chip and Molybdenum than between Molybdenum and bulk Copper.

Abstract: The package parasitics are a serious obstacle to the high-speed switching, which is necessary in order to reduce the switching power losses or reduce the size of power converters. In order to design new packages suitable for Silicon Carbide (SiC) power transistors, it is necessary to extract the parasitics of different packages and be able to predict the switching performance of the power devices placed in these packages. This paper presents two ways of simulating the switching performance in a half-bridge power module with SiC MOSFETs. The results show that the parasitic inductances in the power module slow down the switching, lead to poor current sharing, and together with the parasitic capacitances lead to oscillations. These negative effects can cause failures, increased losses, and electromagnetic compatibility issues.

Abstract: – Thermal contact resistances between a silver metallized SiC chip and a direct bonded copper (DBC) substrate have been measured in a heat transfer experiment. A novel experimental method to separate thermal contact resistances in multilayer heat transfer path has been demonstrated. The experimental results have been compared with analytical calculations and also with 3D computational fluid dynamics (CFD) simulation results. A simplified CFD model of the experimental setup has been validated. The results show significant pressure dependence of the thermal contact resistance but also a pressure independent part.

Abstract: 4H-SiC Schottky Barrier Diodes (SBD) have been developed using p-type buried grids (BGs) formed by Al implantation. In order to reduce on-state resistance and improve forward conduction, the doping concentration of the channel region between the buried grids was increased. The fabricated diodes were encapsulated with TO-254 packages and electrically evaluated. Experimental forward and reverse characteristics were measured in the temperature range from 25 °C to 250 °C. On bare die level, the forward voltage drop was reduced from 5.36 V to 3.90 V at 20 A as the channel doping concentration was increased, which introduced a low channel resistance. By the encapsulation in TO-254 package, the forward voltage drop was decreased approximately 10% due to a lower contact resistance. The on-state resistance of the identical device measured on bare die and in TO-254 package increased with increasing temperature due to the decreased electron mobility in the drift region resulting in higher resistance. The incremental contact resistances of the bare dies were larger than in the packaged devices. One key issue associated with conventional Junction Barrier Schottky (JBS) diodes is a high leakage current at high temperature operation over 200 °C. The developed Buried Grid JBS (BG JBS) diode has significantly reduced leakage current due to a better field shielding at the Schottky contact. The leakage current of the packaged BG JBS diodes is compared to pure SBD and commercial JBS diodes.

Abstract: In this work, we present a planarization concept for epitaxial SiC trench structures involving reactive ion etching (RIE) and inductive coupled plasma (ICP) dry etching. The general idea is to transfer the flat surface from spun-on BCB/photo-resist layers to deposited silicon dioxide and finally to bulk SiC by applying process conditions with the same etch rate for the different materials. In this way several microns of unwanted material can be removed and planar SiC surfaces are obtained. With this method trench structures filled by epitaxial re-growth can be planarized with smooth surfaces and good homogeneity over the wafer. Cost-efficient device manufacturing can be achieved by using standard semiconductor process equipment. This technology makes it possible to manufacture advanced epitaxial SiC material structures for devices such as trench JBS diodes and double-gate trench JFETs.

Abstract: SiC lateral MOSFETs with multi-layers epi-channels were studied in this work. The epi-channel with a high concentration n-type epilayer sandwiched by two lightly doped p-type layers showed a maximum field effect mobility of 17 cm²/V.s, improved from 1.53 cm²/V.s of devices without epi-channels. These devices are normally-off with an average threshold voltage of 1.34V.

Abstract: The 4H-SiC Schottky barrier diodes for high temperature operation over 200 °C have been developed using buried grids formed by implantation. Compared to a conventional JBS-type SBD with surface grid (SG), JBS-type SBD with buried grid (BG) has significantly reduced leakage current at reverse bias due to a better field shielding of the Schottky contact. By introducing the BG technology, the 1.7 kV diodes with an anode area 0.0024 cm² (1 A) and 0.024 cm² (10 A) were successfully fabricated, encapsulated in TO220 packages, and electrically evaluated. Two types of buried grid arrangement with different grid spacing dimensions were investigated. The measured I-V characteristics were compared with simulation. The best fit was obtained with an active area of approximately 60 % and 70 % of the anode area in large and small devices, respectively. The measured values of the device capacitances were 1000 pF in large devices and 100 pF in small devices at zero bias. The capacitance values are proportional to the device area. The recovery behavior of big devices was measured in a double pulse tester and simulated. The recovery charge, Q_c, was 18 nC and 24 nC in simulation and measurement, respectively. The fabricated BG JBS-type SBDs have a smaller maximum reverse recovery current compared to the commercial devices. No influence of the different grid spacing on the recovery charge was observed.