Papers by Author: Pascal Besson

Abstract: A post-etch residue cleaning formulation, based on balancing the aggressiveness of hydrofluoric acid with its well-known residue removal properties is introduced. In a series of investigations originally motivated by the cleaning challenge provided by high-k dielectric-based residues, a formulation platform is developed that successfully cleans residues resulting from the plasma patterning of tantalum oxide and similar materials while maintaining metal and dielectric compatibility. It is further shown that the fundamental advantages of this solution can be extended to the cleaning of other, more traditional post-etch residues, with no sacrifice in compatibility, as demonstrated by measurements on blanket films and through SEM data.

Abstract: Oxidation of a GaAs surface was performed with liquid H₂O₂, gaseous O₂ and O₃ in order to identify the best solution for digital etching. The oxide layer formed with H₂O₂ is Garich and exhibits surface roughening which can be understood by oxide hydrolysis/condensation model. Roughening makes aqueous H₂O₂ irrelevant as an oxidizing agent for repeated oxidation steps. On the other hand, a smooth oxide layer can be obtained with gaseous O₂ and O₃. Thickness of the formed oxide layer is controlled by time exposure to the oxidizing agent. The nature of the oxide was analyzed by XRay Photo-electron Spectroscopy and is also timedependent.

Abstract: Wetting efficiency of microstructures or nanostructures patterned on Si wafers is a real concern in integrated circuits manufacturing. We present here a high-frequency acoustic method which enables the local determination of the wetting state of a liquid on real DTI and TSV structures. Partial wetting states for non-hydrophobic surfaces or low surface tension liquids are detectable with this method. Filling time of TSV structures has also been measured.

Abstract: challenge. Initiated by copper integration for BEOL interconnects the phenomena expanded with the HK / Metal Gate stack use. Therefore, the backside and bevel cleaning became a key parameter to insure both tools integrity and wafers yield while reducing as more as possible the cross contamination risk. The main parameter to avoid the contamination transfer across all the different clean room equipments is to strictly manage the backside and bevel areas on the wafers. Thus, the use of single side processor tools which achieve the specific treatment of the backside and bevel areas drastically increases. Up to now, diluted-HF mixtures are mainly used in production plants demonstrating a good efficiency to remove contamination on dielectric surfaces. Thus, a very large range of contaminant materials can be addressed with a performance level which has been widely evidenced on BEOL applications as well on more FEOL embedded specific materials (ie: Hf, La, W). Nevertheless, the fundamental mechanism which drives the diluted-HF mixtures efficiency remains only based on a lift-off effect as the contaminant can be caught in the liquid phase after a fixed amount material etching. Most of the time there is no direct solubilisation of the contaminant from the surface. For silicon surface without any dielectric coverage the efficiency of a single diluted HF mixture can be very poor especially towards noble metals contamination. Various on-going developments (ie on MRAM technology or 3D integration or Imagers) in which pure FEOL tools are used on MEOL or BEOL levels required more efficient cleaning towards a larger range of metal contamination on backside and bevel areas.

Abstract: III-V semiconductor compounds are increasingly studied for their interesting properties in the fields of microelectronics, optoelectronics, infrared detectors or solar cells. Firstly, they are promising candidates to replace silicon as a channel material. As CMOS scales beyond the 22 nm node it is widely expected that new higher mobility channel materials such as In_xGa_1-xAs will have to be introduced [1]. On the other hand, III-V materials have a direct bandgap making them useful for optoelectronic devices or high-efficiency multijunction photovoltaic cells. For these applications InP, GaAs and their alloys as In_xGa_1-xAs and Ga_xIn_1-xP are investigated [2]. Depending on the targeted applications, several possible integration routes of III-V components could be considered: from 100 mm III-V substrates to III-V epitaxial layers grown on 300 mm silicon wafers as well as a few square centimetres chips bonded on 200 or 300 mm carrier wafers for photonics applications. In all cases, the manufacturing of devices requires a multitude of wet chemical steps including selective etching steps (from a few nanometres up to several microns) and cleaning steps (metallic or particles contamination removal).

Abstract: More and more, 300mm manufacturing promotes a single wafer tool approach in FEOL cleaning. Previously, we reported an advanced surface preparation process based on dilute HF/HCl/DIW and O3/HCl/DIW chemistries coupled with megasonic activation during the ozone step only, on a 300mm single-wafer platform [1]. As throughput consideration implies shorter process time, the activation of megasons during the whole cleaning step could be of interest for very small particle removal efficiency. Nevertheless, extending megasonic activation to the entire process sequence leads to degraded results on silicon surface. Indeed, damages are created at 90 and 65nm defect inspection levels when megasonic activation is used in the presence of both HF species and on hydrophobic silicon surface. In this paper, we demonstrate that the megasonic activation (Megs) generates randomly and locally oxidized species which may be the main cause of damages in the presence of HF chemistry. Additional characterizations are performed to understand this problem (haze inspections, ATR analysis and contact angle measurements).

Abstract: This paper summarizes the process development of TiN barrier etching in presence of copper, for a thick copper level in BICMOS technology. In an industrial context, we have chosen to use a SC1 chemistry in a spin etch single wafer tool. The SC1 composition and therefore the pH level allows - the barrier to be etched with no metallic residues, ( if not clear this can be a source for shorts) - control of the selectivity between copper and TiN - control of lateral etching under copper lines, the possible source of open chains by W attack during TiN etch. The electrical results show a robust process according to current specifications, in terms of leakage and via resistance with a fresh chemistry approach. In fact, the recirculation of SC1 is not possible due to substantial concentration changes during processing, high evaporation rate of Ammonia and high decomposition rate of Peroxide in the presence of copper on surface wafer.