Papers by Author: Patrick Berwian

Abstract: Point defects in 4H silicon carbide (4H-SiC), such as the silicon vacancy, also known as color centers, offer considerable potential for quantum applications in the fields of quantum sensing as well as computing and communication. The latter two necessitate indistinguishable photons for entanglement swapping and consequently demand precise control over the electronic transition energies, i.e. emission and absorption wavelengths of color centers. One way to achieve this is through monolithic integration of electronic devices in combination with integrated photonics in 4H-SiC. This is considered a potential pathway for scalable quantum photonic integrated circuits. In this paper, we investigate the suitability of a signal-ground-modulator and a vertical pin diode in combination with a waveguide to (i) achieve local field strengths of 5 to 20 MV/m in the crystal’s c-direction, (ii) stabilize the charge state of the silicon vacancy by controlling the local Fermi level, (iii) meet the requirements for photonic single-mode operation, and (iv) minimize the absorption of the evanescent wave due to metal contacts. The findings of the electronic and optical simulations conducted with Synopsys Sentaurus and Ansys Lumerical suggest that the signal-ground-modulator, commonly used in integrated photonics, rarely attains the requisite field strength. In contrast, the vertical pin diode has the potential to meet these requirements even at reduced bias voltages. Furthermore, the intrinsic layer of the diode offers a wide region in which to host the color center in its optically active, negatively charged state.

Abstract: Two fully loaded epitaxial growth runs with 16 wafers in total were conducted in the AIXTRON G5 WW reactor in order to keep epigrowth conditions constant. The wafers were selected with a large spread of specific resistivity and dislocation densities. The resulting epilayers showed very good intra-wafer homogeneities as well as excellent wafer-to-wafer and run-to-run reproducibility with regard to epilayer thickness and doping concentration, point defect concentrations of Z_1/2 and EH_6/7 and the resulting Shockley-Read-Hall carrier lifetime. We found that the dislocation densities of the underlying substrates are influencing the stacking fault densities of the epilayers, which then vary between 0.1 and 10 cm^-2. A substrate effect on the effective minority carrier lifetime was found.

Abstract: Temperature dependent microwave detected photoconductivity MDP and time-resolved photoluminescence TRPL were employed to investigate the carrier lifetime in CVD grown 4H-SiC epilayers of different thickness. The minority carrier lifetime may be found from both theMDP and defect PL decay at room temperature for all epilayers, whereas the near bandedge emission (NBE) decay is much faster for thin epilayers (<17 μm) due to the substrate proximity and only follows the minority carrier lifetime for thicker samples at lower excess carrier concentrations.

Abstract: The development of bipolar 4H-SiC devices for high blocking voltages requires the growth of high carrier lifetime epitaxial layers with low Z_1/2 concentrations. This paper shows a comprehensive investigation of the influence of epitaxial growth parameters (C/Si ratio and growth temperature) on Z_1/2 concentration and minority carrier lifetime. On the basis of a discovered exponential correlation of Z_1/2 with the C/Si ratio and growth temperature, a competitive low Z_1/2 concentration of 1.9∙10¹² cm^-3 could be achieved by lowering the growth temperature and switching to higher C/Si ratio. Thermodynamic considerations by an Arrhenius approach reveal a dependency of the formation enthalpy of Z_1/2 on the thermal process and process conditions of the epitaxial growth. Furthermore, the correlation between Z_1/2 and the effective minority carrier lifetime confirms the occurrence of a necessary second recombination mechanism beside the common recombination at deep levels by Shockley-Read-Hall for low Z_1/2 concentration.

Abstract: Electrical testing with regard to bipolar degradation of high voltage SiC devices cannot be done on wafer level, but only expensively after module assembly. We show that 4H-SiC material can be optically stressed by applying high UV laser intensities, i.e. bipolar degradation as in electrical stress tests can be provoked on wafer level. Therefore, optical stressing can be used for control measurements and reliability testing. Different injection (=stress) levels have been used similar to the typical doping level of the base material and similar to the established electrical stress test. The analysis of degradation is done by photoluminescence imaging which is a well-established technique for revealing structural defects such as Basal Plane Dislocations (BPDs) and stacking faults (SFs) in 4H-SiC epiwafers and partially processed devices.

Abstract: We present an extended model for the simulation of the effective minority carrier lifetime in 4H-SiC epiwafers after optical excitation. This multilayer model uses measured values (such as doping profile, point defect concentration and capture cross sections, epilayer thickness) as input parameters. The bulk lifetime and the diffusion constant are calculated from the actual time dependent excess carrier profiles, resulting in more realistic transients having different decay regimes than in other models. This enables a better understanding of optical lifetime measurements.

Abstract: A new tool for characterizing extended defects in Silicon Carbide (SiC) based on photoluminescence imaging is presented. In contrast to other techniques like Defect Selective Etching (DSE) or X-ray topography this technique is both fast and non-destructive. It is shown that several defect types, especially those relevant for the performance of electronic devices on SiC (i.e. Stacking Faults and Basal Plane Dislocations) can be investigated. The tool is therefore usable in research and development for a quick feedback on process related defect generation as well as in a production environment for quality control.

Abstract: This work shows thermal simulations of a package of 48/96 high-voltage (6.5 kV/1 kA) PiN diodes. A temperature dependent heat generation for a forward voltage of 3.6 V with a realistic heat generating volume in the diode of (2.7x2.7x0.01) mm3 was used. The thermal coupling of two diodes was determined to be less than 1 % for a distance between the diodes of 10 mm. The temperature distribution for the entire module has been studied for two different ceramic insulating materials, AlN and Al₂O₃, as well as for two numbers of diodes, 48 and 96. This led to a maximum temperature of 106 °C/118 °C (AlN, 48/96 diodes) and 123 °C/144 °C (Al₂O₃, 48/96 diodes). Assuming a constant applied voltage, a variance of ±0.5 V of the characteristic curve (forward voltage versus current) due to variations in the production process was considered fork single diodes. For a shift of +0.5 V for a single diode, the maximum temperature difference to the cooler temperature becomes approximately twice the original difference. Additionally, the operation under constant current (7.1 A, 10.2 A, 14.2 A) was studied including single diode failure. For single diode failure, the resulting change of the maximum temperature would be less than 3 %.

Abstract: The addition of hydrogen chloride (HCl) to our conventional CVD process allows for high growth rates up to 50 μm/h while maintaining the step-flow growth mode. Such epilayers exhibit quite low total concentrations of point defects less than 2 x 10¹³ cm^-3. But, the HCl addition shows an ambivalent influence on the concentration of the lifetime killer defect Z_1/2. For low growth rates, the Z_1/2 concentration slightly decreases with increasing HCl addition. For higher growth rates, the Z_1/2 concentration increases with increasing HCl addition.

Abstract: 4H-SiC PiN diodes for 6.5 kV were manufactured on both 4° and 8° off-cut substrates and subjected to an electrical stress test on wafer level and subsequent analysis of structural defects present in the active area of the diodes. For 8° off-cut diodes, the electrical characteristics with respect to leakage current and forward voltage drift are worse than the electrical characteristics of 4° off-cut diodes. Furthermore, a large number of stacking faults was found in 8° off-cut diodes, but little evidence for bipolar degradation was found in 4° off-cut diodes. Therefore, bipolar degradation was significantly reduced by avoiding BPDs in the active area of PiN diodes, i.e. by the use of 4° off-cut substrates. Furthermore, a strong correlation was found between the electrical screening test on wafer level and critical defects.