Papers by Author: Philippe Absil

Abstract: We report in this work some process optimization effort in performing poly silicon removal for replacement gate process integration. Successful wet poly silicon removal after dummy gate patterning is not only conditioned by suitable process conditions during wet removal but is also impacted by process steps prior to gate removal A thorough evaluation of the impact on poly removal from dopants or contaminants introduced in the poly silicon by previous processing is done, resulting in an optimized integration flow with successful poly removal. This work also shows that use of diluted TMAH chemistry instead of diluted ammonia in performing poly silicon removal provides better ability in removing poly silicon especially in narrow gate structures.

Abstract: With the continuous down scaling features sizes, the need of speed increase and power consumption reduction start to be more and more critical. The classical integration scheme of poly silicon gate on CMOS devices does not meet the requirements of the 45 nm technology node and beyond. On this matter, new materials and different integration flows are being investigated in order to improve the device performance. High-k materials associated with metals are actively investigated as new gate materials in which different integration approaches like metal gate first or metal gate last are proposed [1].