Authors: Dominique Planson, Camille Sonneville, Pascal Bevilacqua, Pierre Brosselard, Mihai Lazar, Sigo Scharnholz, Bertrand Vergne, Hervé Morel
Abstract: This paper presents for the first time a comparison between experimental measurements of Optical Beam Induced Current (OBIC) and finite element simulations on high-voltage bipolar diodes. Two peripheral protection structures were chosen: a simple MESA protection and a MESA + JTE combination. Comparable experimental and simulated results were obtained in both cases.
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Authors: Pierre Brosselard, Brenda Fosso-Sob, Dominique Planson, Pascal Bevilacqua, Camille Sonneville, Mihai Lazar, Bertrand Vergne, Sigo Scharnholz, Hervé Morel
Abstract: In this paper, the static and dynamic characterization of a High Voltage (10kV) 4H-SiC Bipolar Junction Transistor (BJT) is presented. Using a high-voltage source in vacuum conditions, a breakdown voltage of 11 kV was measured. Results showed that both large and small BJTs exhibit similar on-state resistance per unit area and collector current density of 55 A.cm-2. The current gain increases with a decrease in temperature, indicating reduced charge carrier recombination at lower thermal energies. Also, BJT have been characterized in switching mode at 1 kV. The study concludes that 4H-SiC BJT demonstrates promising electrical performance for high-efficiency applications in harsh environments.
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Authors: Dominique Tournier, Thomas Vadebout, Pascal Bevilacqua, Pierre Brosselard, Jean François de Palma
Abstract: Fault protection of AC and DC network using semiconductors requires accurate electrothermal design of active and passive devices to keep power losses low in nominal condition and to sustain high current overload. Using SiC MOSFET for SSPC arises challenges to keep power losses low and to ensure robustness versus abnormal operating condition. Indeed, unpredictable events can dramatically damage the device integrity such as current overload, short-circuit... To overcome those issues, ones are generally carefully design driving system, implementing sensors and fast digital control circuit computing to sense simultaneously current, voltage and temperature, to analyze and detect abnormal operating condition. To reduce the whole detection transmission and reaction chain, we have designed a 1200V ; 30A ; 65mΩ instrumented SiC MOSFET, including both a current mirror and a temperature sensor in the active area of the die. This paper reports for the first-time real-time SiC instrumented MOSFET temperature and current measurement without the need of external sensors nor estimators.
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Authors: Pierre Brosselard, Dominique Planson, Dominique Tournier, Pascal Bevilacqua, Camille Sonneville, Luong Viet Phung, Mihai Lazar, Bertrand Vergne, Sigo Scharnholz, Hervé Morel
Abstract: In this paper, a first demonstration of the optical triggering of a 10 kV 4H-SiC Bipolar Junction Transistor is reported. A laser emitting UV (349 nm) has been used for the generation electron-hole pairs within the device. A current density of about 20 A.cm-2 has been obtained. This low value in comparison with 100 A.cm-2 for “conventional” BJT is due to the narrow pulse width (5 ns). The current waveform shows the effect of the carrier lifetime in the base and collector regions. From these measurements, we have extracted the IC (VCE) characteristics for different laser optical power and the switch-on time which is about 1 µs.
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Authors: Dominique Planson, Dominique Tournier, Pascal Bevilacqua, Camille Sonneville, Pierre Brosselard, Gabrielle Moulin, Luong Viet Phung, Philippe Godignon
Abstract: This paper presents micro-OBIC measurements performed at different biasing on two power devices protected by a combination of P+ rings embedded in a JTE Zone. Thanks to the micro-OBIC micrometer spatial resolution, small gaps can be visible on OBIC profiles. Thus, the spatial variation of the micro-OBIC signal accurately reflects the topology of the periphery protection: combination of JTE and rings and channel stopper. These measurements agree with the electric field distribution (calculated by finite element method) along the structure.
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Authors: Konstantinos Zekentes, Antonis Stavrinidis, George Konstantinidis, Maria Kayambaki, Konstantinos Vamvoukakis, Emmanouil Vassakis, Konstantin Vasilevskiy, Alton B. Horsfall, Nick G. Wright, Pierre Brosselard, Shi Qin Niu, Mihai Lazar, Dominique Planson, Dominique Tournier, Nicolas Camara, Matthias Bucher
Abstract: Trenched-implanted-gate 4H–SiC vertical-channel JFET (TI-VJFET) have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. The effect of the channel geometry on the electrical characteristics has been studied by varying its length (0.3 and 1.2μm) and its width (1.5-5μm). The transistors exhibited high current handling capabilities (Direct Current density 330A/cm2). The output current reduces with the increase of the measurements temperature due to the decrease of the electron mobility value. The voltage breakdown exhibits a triode shape, which is typical for a static-induction transistor operation.
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Authors: Pierre Brosselard, Florian Chevalier, Benjamin Proux, Nicolas Thierry-Jebali, Pascal Bevilacqua, Dominique Tournier, Dominique Planson, Gregory Grosset, Lionel Dupuy
Abstract: This work reports on the fabrication and electrical characterization of 3 different diodes. The first one is a Schottky diode with a single 50 mm P+ ring between the edge termination and the active area. The two other diodes are JBS with a 3 mm P+ strips separated by 4 mm and 8 mm respectively. The breakdown voltage ranges from 2.7kV up to 3.7kV depending on the P+/N area. The 3 different diodes exhibit a similar on-resistance versus the temperature behavior. Moreover, no contribution of the bipolar conduction is observed and no degradation has been observed when a forward stress is performed in forward mode and also in reverse.
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Authors: Nicolas Thierry-Jebali, Arthur Vo-Ha, Davy Carole, Mihai Lazar, Gabriel Ferro, Hervé Peyre, Sylvie Contreras, Pierre Brosselard
Abstract: This work reports on the improvement of ohmic contacts made on heavily p-type doped 4H-SiC epitaxial layer selectively grown by Vapor-Liquid-Solid (VLS) transport. Even before any annealing process, the contact is ohmic. This behavior can be explained by the high doping level of the VLS layer (Al concentration > 1020 cm-3) as characterized by SIMS profiling. Upon variation of annealing temperatures, a minimum value of the Specific Contact Resistance (SCR) down to 1.3x10-6 Ω.cm2 has been obtained for both 500 °C and 800 °C annealing temperature. However, a large variation of the SCR was observed for a same process condition. This variation is mainly attributed to a variation of the Schottky Barrier Height.
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Authors: Nicolas Thierry-Jebali, Mihai Lazar, Arthur Vo-Ha, Davy Carole, Véronique Soulière, Anne Henry, Dominique Planson, Gabriel Ferro, Leszek Konczewicz, Sylvie Contreras, Christian Brylinski, Pierre Brosselard
Abstract: This work deals with two applications of the Selective Epitaxial Growth of highly p-type doped buried 4H-SiC in Vapor-Liquid-Solid configuration (SEG-VLS). The first application is the improvement of the Specific Contact Resistance (SCR) of contacts made on such p-type material. As a result of the extremely high doping level, SCR values as low as 1.3x10-6 Ω.cm2 have been demonstrated. Additionally, the high Al concentration of the SEG-VLS 4H-SiC material induces a lowering of the Al acceptor ionization energy down to 40 meV. The second application is the fabrication of PiN diodes with SEG-VLS emitter and guard-rings peripheral protection. Influence of some process parameters and crystal orientation on the forward and reverse characteristics of the PiN diodes is discussed.
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Authors: Matthieu Florentin, Josep Montserrat, Pierre Brosselard, Anne Henry, Philippe Godignon
Abstract: This paper deals with the comparison of several MOS structures with different rapid thermal oxidation processes (RTO) carried out on Off and On-axis SiC material. A first set contains MOS capacitance structures on n-epitaxial layers, while a second set of MOS capacitance are built on p-implanted layers. Both sets include On and Off-Axis angle cuts. Furthermore, n-MOSFETs have been fabricated on On-axis p-implanted layers with the best oxidation process selected from the MOS capacitance study. The final objective is to show the performances of these On-axis p-implanted n-MOSFETs and to evidence the associated lower surface roughness at the SiO2/SiC interface.
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