Papers by Author: Qing Chun Jon Zhang

Abstract: The effects of Shockley stacking faults (SSFs) that originate from half loop arrays (HLAs) on the forward voltage and reverse leakage were measured in 10 kV 4H-SiC PiN diodes. The presence of HLAs and basal plane dislocations in each diode in a wafer was determined by ultraviolet photoluminescence imaging of the wafer before device fabrication. The SSFs were expanded by electrical stressing under forward bias of 30 A/cm², and contracted by annealing at 550 °C. The electrical stress increased both the forward voltage and reverse leakage. Annealing returned the forward voltage and reverse leakage to nearly their original behavior. The details of SSF expansion and contraction from a HLA and the effects on the electrical behavior of the PiN diodes are discussed.

Abstract: A novel power device configuration, the Bipolar Turn Off thyristor (BTO), was proposed and demonstrated in SiC. The BTO operates in anode switch configuration consisting of a 9 kV SiC p-type Gate Turn Off thyristor (GTO) and a 1600 V SiC n-type Bipolar Junction Transistor (BJT). Compared with SiC GTOs, several new features have been accomplished in the BTO: (1) A positive temperature coefficient of forward voltage drop, (2) Anode current saturation capability, and (3) A simple gate driver and fast switching speed.

Abstract: 4H-SiC Bipolar Junction Transistors (BJTs) and hybrid Darlington Transistors with 10 kV/10 A capability have been demonstrated for the first time. The SiC BJT (chip size: 0.75 cm2 with an active area of 0.336 cm2) conducts a collector current of 10 A (~ 30 A/cm2) with a forward voltage drop of 4.0 V (forced current gain βforced: 20) corresponding to a specific on-resistance of ~ 130 mΩ•cm2 at 25°C. The DC current gain, β, at a collector voltage of 15 V is measured to be 28 at a base current of 1 A. Both open emitter breakdown voltage (BVCBO) and open base breakdown voltage (BVCEO) of ~10 kV have been achieved. The 10 kV SiC Darlington transistor pair consists of a 10 A SiC BJT as the output device and a 1 A SiC BJT as the driver. The forward voltage drop of 4.5 V is measured at 10 A of collector current. The DC forced current gain at the collector voltage of 5.0 V was measured to be 440 at room temperature.

Abstract: In this paper, for the first time, we report a large area (1 cm2) SiC GTO with 9 kV blocking voltage fabricated on 100-mm 4H-SiC substrates with much reduced Basal Plane Dislocation (BPD) density. The static and dynamic characteristics are described. A forward drop of 3.7 V at 100 A (100 A/cm2) is measured at 25°C. A slight positive temperature coefficient of the forward drop is present at 300 A/cm2, indicating the possibility of paralleling multiple devices for higher current capability. The device exhibits extremely low leakage currents at high temperatures. The device has shown fast turn-on time of 53.9 nsec, and ~3.5 s of turn-off time, respectively. A stable forward voltage drop after electrical stress for >1000 hours has been achieved.

Abstract: In this paper, we review the performance, reliability, and robustness of the current 4H-SiC power DMOSFETs. Due to advances in device and materials technology, high power, large area 4H-SiC power DMOSFETs (1200 V, 67 A and 3000 V, 30 A) can be fabricated with reasonable yields. The availability of large area devices has enabled the demonstration of the first MW class, all SiC power modules. Evaluations of 1200 V 4H-SiC DMOSFETs showed that the devices offer avalanche power exceeding those of commercially available silicon power MOSFETs, and have the sufficient short circuit robustness required in most motor drive applications. A recent TDDB study showed that the gate oxides in 4H-SiC MOSFETs have good reliability, with a 100-year lifetime at 375oC if Eox is limited to 3.9 MV/cm. Future work on MOS reliability should be focused on Vth shifts, instead of catastrophic failures of gate oxides.

Abstract: The influence of stacking fault (SF) generation on the reverse blocking characteristics has been investigated on SiC 10 kV, 5 A Merged PiN (MPS) diodes. For the first time, we have observed that the generation of SFs under forward biased stress increases the reverse leakage current. In addition, the presence of a secondary diode formed by the electrical stress was observed and attributed to the breakdown voltage failure on certain devices.

Abstract: In this work the analysis of thermal diffusion of boron carried out from vapor phase was performed. Two-branch diffusion associated with kick-out and substitution mechanisms was observed. The activation energy and prefactor were calculated from Arrhenius plot for each diffusion branch. It has been established that the surface layer of diffused boron mostly consists of shallow boron acceptors, while the tail of the diffusion profile has mostly deep level D centers.

Abstract: This paper presents the effect of recombination-induced stacking faults on the drift based forward conduction and leakage currents of high voltage 4H-SiC power devices. To show the effects, IV characteristics of a 4H-SiC 10 kV DMOSFET and a 4H-SiC 4 kV BJT have been evaluated before and after the induction of stacking faults in the drift epilayer. For both devices, significant increases in forward voltage drops, as well as marked increases in leakage currents have been observed. The results suggest that injection of minority carriers in majority carrier devices should be avoided at all times.

Abstract: SiC IGBTs are suitable for high power, high temperature applications. For the first time, the design and fabrication of 9 kV planar p-IGBTs on 4H-SiC are reported in this paper. A differential on-resistance of ~ 88 m(cm2 at a gate bias of –20 V is achieved at 25°C, and decreases to ~24.8 m(cm2 at 200°C. The device exhibits a blocking voltage of 9 kV with a leakage current density of 0.1 mA/cm2. The hole channel mobility is 6.5 cm2/V-s at room temperature with a threshold voltage of –6.5 V resulting in enhanced conduction capability. Inductive switching tests have shown that IGBTs feature fast switching capability at both room and elevated temperatures.

Abstract: Optimization of the thermally oxidized 4H-SiC MOS interface has produced p-channel lateral MOSFETs with hole inversion layer mobility as high as 10 cm2/Vs. This has been accomplished by identifying the 1200oC Dry, 950oC Wet (un-nitrided) oxidation as ideal for hole conduction across the MOS inversion layer and by implant activation annealing at 1800oC of the heavily implanted n-type well. High temperature measurements show that the high mobility and normally-off operation is maintained throughout the operating temperature range. Oxide leakage measurements yield a dielectric strength of 8.5 MV/cm with 90% yield, thereby enabling the manufacture of high performance p-channel devices like the IGBT.