Papers by Author: Robert E. Stahlbush

Abstract: Silicon carbide is a leading wide-bandgap semiconductor for high-voltage power electronics. For 6.5–10 kV operation, thick epitaxial layers (≥60 µm) are required to sustain depletion width and maintain uniform electric fields, placing a premium on low extended-defect densities in both substrate and epilayer. Thick epitaxial 4H-SiC layers of 60 µm and 110 µm were grown on 6-inch substrates in a multi-wafer warm-wall reactor and evaluated by synchrotron X-ray topography in grazing-incidence (22-4 16) and transmission (11-20) geometries. Transmission imaging showed substrate dislocation content near the lower bound typically reported for 6-inch wafers. Notably, grazing-incidence topography (penetration depth >40 µm) revealed no basal-plane dislocations propagating into the epilayers, consistent with efficient dislocation conversion at the substrate–epilayer interface. The 3C-SiC inclusion density was ~30 per 6-inch wafer for 60 µm epilayers and ~60 per wafer for 110 µm epilayers; the average micropipes density varies from 0 to 5 for both 60 and 110 um epiwafers. Threading dislocation densities—screw, edge, and mixed—were on the order of 1.0–2.0 × 10³ cm⁻². These results establish thick 4H-SiC epilayers with suppressed basal-plane propagation and substantially reduced extended-defect content, providing a strong basis for reliable 6.5–10 kV device fabrication.

Abstract: Implantation process for high Al dose p+ contact layers in SiC MOSFETs can generate new basal plane dislocations (BPDs). Such BPD faulting under high carrier injection was investigated in SiC MOSFET layers designed for 3.3kV operation with either room temperature (RT) or high temperature (HT) implantations performed for their high dose p+ contact layer. For excess carrier injection levels of ~1x10¹⁸ cm^-3 implant induced BPDs faulted from the termination regions of the MOSFETs in the case of RT samples, while the HT samples show no BPD faulting because there were no implant-induced BPDs. However, in the active region of the device no BPDs faulted for both the RT as well as HT samples even at a higher carrier injection of ~1x10¹⁹ cm^-3. Technology computer-aided design (TCAD) simulations show that the lower doped p-well region below the p+ contact in the active area of the device prevents the minority electron density in the p+ contact layer to below 10x the hole density, which limits BPD faulting even when they are present in that layer as in the case of RT implanted samples.

Abstract: Depth profiling of the ambipolar carrier lifetime was performed in n-type, 140mm thick silicon carbide (SiC) epilayer using excitation by two-photon absorption (TPA) with a pulsed 586nm laser, and confocal measurement of time resolved photoluminescence (TRPL) decay from the excited region. A depth resolution of ≈10mm was obtained. The PL decay curves were analyzed using a recently developed formalism that takes into account the TPA excitation, carrier diffusion and surface/interface recombination. The carrier lifetime decreases near the top surface of the epitaxial layer as well as near its interface with the substrate.

Abstract: Basal Plane Dislocations (BPD) intersecting the SiC substrate surface were converted to threading edge dislocations (TED) by high temperature annealing of the substrates in the temperature range of 1750 °C – 1950 °C. Successively, epitaxial growth on annealed as well as non-annealed samples was performed, concurrently, to investigate the effect of the substrate annealing on BPD mitigation in the epilayers. For the 1950 °C/10min anneal, a 3x reduction in BPD density was observed. Additionally, surface roughness measured using atomic force microscopy revealed no degradation in surface morphology of the grown epilayers after annealing.

Abstract: Basal plane dislocations (BPDs) introduced into SiC epitaxial layers, 25 μm thick, by the combination of implantation and activation anneal are directly observed by ultraviolet photoluminescence (UVPL) imaging. BPD loops appear to originate at micron-sized or smaller areas at the surface. These loops expand by gliding along the basal plane in the offcut direction until the loops approach the substrate. The loops can glide perpendicular to the offcut direction by many millimeters.

Abstract: Basal Plane Dislocations (BPD) were reduced in 4H-SiC epilayers by high temperature annealing in the range of 1600 °C to 1950 °C using two annealing techniques. Samples annealed at > 1750 °C showed almost complete elimination of BPDs propagating from the substrate. However, surface morphology was degraded for MW annealed samples above 1800 °C, with new BPDs being generated from the surface. A new capping technique was developed along with application of high N₂ overpressure to preserve the surface morphology and avoid formation of new BPDs.

Abstract: Suppression of basal plane dislocations (BPDs) from critical epitaxial drift layer has occurred mainly by converting BPDs in the substrate into threading edge dislocations before the BPDs enter the drift layer. As optimized epitaxial growth has produced drift layers free of BPDs originating from the substrate over a large fraction of the wafer, other sources of BPDs have become important. One source of BPDs introduced during epitaxial growth is from inclusions, which mainly consist of misoriented 4H-SiC. Inclusions are surrounded by a local cluster of BPDs and in thick, low-BPD epitaxy the outermost BPDs glide centimeters from the inclusion forming a much larger damaged area. The details of BPD migration from inclusions are discussed.

Abstract: The effects of Shockley stacking faults (SSFs) that originate from half loop arrays (HLAs) on the forward voltage and reverse leakage were measured in 10 kV 4H-SiC PiN diodes. The presence of HLAs and basal plane dislocations in each diode in a wafer was determined by ultraviolet photoluminescence imaging of the wafer before device fabrication. The SSFs were expanded by electrical stressing under forward bias of 30 A/cm², and contracted by annealing at 550 °C. The electrical stress increased both the forward voltage and reverse leakage. Annealing returned the forward voltage and reverse leakage to nearly their original behavior. The details of SSF expansion and contraction from a HLA and the effects on the electrical behavior of the PiN diodes are discussed.

Abstract: Shockley stacking fault (SSF) contraction in 4H-SiC was investigated, in-situ, under varying temperature and ultraviolet (UV) intensity. Contraction of single SSFs at room temperature was observed for the first time under low power UV excitation of 0.04 W/cm². At temperatures above 150 °C, complete SSF contraction occurred for UV power at 0.2 W/cm². In contrast to expansion, SSF contraction occurred in discrete jumps between pinning sites along existing C-core partials. Luminescence from the pinning sites suggest they may be local concentrations of point defects. Additionally, a change in the line direction of the Si-core partials by ~25o off the direction was observed.

Abstract: The effect of extended defects on carrier lifetime was investigated in 140 um thick 4H-SiC epilayers using whole wafer ultraviolet photoluminescence (UVPL) and microwave photoconductive decay (uPCD) mapping. Half-loop arrays (HLA) seen in the UVPL images showed a corresponding lifetime degradation in the same region, even before expansion of the HLAs to form SFs. Lifetime lowering was also seen for a defect comprising of a small 3C-SiC inclusion with a larger misoriented 4H-SiC region. Additionally, formation of slip planes after high temperature annealing was observed, which consequently shows a lifetime reduction in that region.