Papers by Author: Roland Rupp

Abstract: We studied the impact of ion implantation into the wafer substrate prior to the epitaxy process on the basal plane dislocation conversion behavior during epitaxial layer growth. Defect density measurements show an enhancing effect of the ion implantation on the basal plane dislocation to threading edge dislocation conversion. Analysis of the lateral conversion distribution, the stress field in the material as well as the wafer topography at the onset of epitaxial growth lead us to believe, that stresses in the epitaxy layer cause the enhanced basal plane dislocation conversion.

Abstract: The incorporation of Germanium (Ge) in 4H-SiC has recently being reported as enabling an increase of the electron mobility in n-type doped layers. The present work aims at evaluating the impact of the Ge doping on two types of SiC devices: Merged PiN-Schottky (MPS) diodes and Trench MOSFETs.

Abstract: We report on the development of a new generation of SiC Schottky rectifier devices employing a Molybdenum based barrier metal system and a new stripe cell design for field shielding and optimized area utilization. The Schottky barrier height is reduced and thus the conduction losses are decreased significantly. The balance between forward conduction and reverse leakage losses as well as the homogeneity and stability of the new barrier system are investigated carefully.

Abstract: In this paper, an investigation into the crystal structure of Al-and N-implanted 4H-SiC is presented, encompassing a range of physical and electrical analysis techniques, with the aim of better understanding the material properties after high-dose implantation and activation annealing. Scanning spreading resistance microscopy showed that the use of high temperature implantation yields more uniform resistivity profiles in the implanted layer; this correlates with KOH defect decoration and TEM observations, which show that the crystal damage is much more severe in room temperature implanted samples, regardless of anneal temperature. Finally, stress determination by means of μRaman spectroscopy showed that the high temperature implantation results in lower tensile stress in the implanted layers with respect to the room temperature implantation samples.

Abstract: A new method for homogenous drift layer doping is introduced. Instead of in-situ doping during epitaxial growth a subsequent high energy ion implant step is used to dope the drift layer of 650V MPS (Merged-PN-Schottky) diodes. In order to avoid multiple implant steps with various energies for emulating a box-like doping profile, a novel “energy filter” membrane is used to transform the monochromatic ion beam to a beam with a continuous energy spectrum suited for box-like doping. The electrical characteristics of the diodes manufactured by this means show a very homogenous blocking behavior on wafer level, however the expected improved homogeneity in differential resistance of the wafers could not be confirmed by wafer level measurements. More work is needed to understand this discrepancy between experiment and theory.

Abstract: Infineon’s 5^th Generation of 1200V SiC diodes uses a new compact chip design, realized by an optimized hexagonal merged-pn cell structure in the active area. This allows a higher n-doping in the epi layer due to improved E-field shielding resulting in a smaller differential resistance per chip area. Thanks to the merged-pn cell structure, depending on the diode ampere rating, a surge current capability now rated up to 14 times the nominal current ensures robust diode operation during surge current events in the application. The previous generations of 1200V SiC diodes could not make full use of the high breakdown field strength of the SiC material due to the instable avalanche which occurs at the edge termination only, and therefore, requiring a significant safety margin between rated voltage and breakdown voltage. Now the 5^th Generation is designed in a way that each cell contributes to the avalanche, enabling a much more avalanche rugged device.

Abstract: This paper presents for the first time a 650V SiC JFET switch. Although this application class is highly competitive and occupied by Silicon devices the characterization data show unique features which make the SiC switch an outstanding option for future system integration.

Abstract: A significant performance gain of 650V SiC diodes is possible by reducing the wafer thickness from the standard thickness of 350 µm to < 150 µm. Not only the differential resistance of the diodes but also the Rth benefit from this chip thickness reduction. As consequence a further chip size reduction with accompanying capacitive charge reduction leads to a device with improved efficiency in PFC applications under both high load and low load conditions.

Abstract: The forward current distribution in SiC 600V merged pn-Schottky (MPS) diodes is visualized with the help of emission microscopy at various current densities. It is shown how the light emission develops with increasing current densities and extends from the Schottky contact areas into the pn junction areas. Large p⁺-regions e.g. in the edge termination contribute first by minority carrier injection, whereas the smaller p⁺ hexagonal cells and the p⁺ grid follow subsequently.

Abstract: In this paper we compare the thermal behavior of identical SiC Schottky diodes mounted in i) a standard TO220 package (TO220) with non-isolated backside applying standard soft solder and diffusion solder die attach with ii) a so called FULLPAK TO220 package (TO220FP, only diffusion soldering). Depending on the solder technique the heat transport from the junction area of the SiC Schottky diode to the heat sink or to the package backside is improved for the diodes mounted via diffusion solder. For small chips this holds even for TO220FP in comparison to TO220 with standard solder. Simulations of the vertical temperature distribution after electrically heating with a half sine wave for 10ms up to 190W show a decrease of the maximal junction temperature of the SiC Schottky diode from TJ=260 °C to TJ=180 °C if the diffusion solder is used independent from the package type.