Papers by Author: Sang Kwon Lee

Abstract: In this work, SiC nanowire (NW) FETs are prepared and their electrical measurements are presented. From the samples fabricated on the same substrate, various I-Vs shapes are obtained (linear, non linear symmetric, and asymmetric). With the assistance of simulation, we show that this is a result of different values of Schottky Barrier Heights (SBH) at Source (S) / Drain (D) contacts of FETs. An origin for this might be a non uniformity in annealing, NW doping level and high interface traps density (that pins the Fermi level) as well as the high sensitivity of the metal-NW contacts to local surface contaminations.

Abstract: We report on investigation of the AC dielectrophoresis aligned assembly deposition (DAAD) of gallium nitride nanowires (GaN NWs) with both the variation of the electric field and the frequency. Our DAAD methods were used to align and manipulate GaN nanowires as well as to extract the electrical properties of semiconducting nanowires. We observed that the ability of the alignment strongly depends on the magnitude of the AC electric field and frequencies. For the higher AC peak-to-peak electric fields (up to 20 Vp-p), the GaN nanowires have a better alignment across the patterned Ti / Au electrodes with a high yield rate of ~ 90% over the entire arrays (in our case, 20 arrays) in the chip at the 20 kHz. From the transport measurements of our AC aligned GaN nanowires using conventional three-probe schemes in field-effect transistor structures, we found that the conductance of the GaN NWs increased for gating voltage greater than zero and decreased for gating voltage less than zero, indicating these GaN nanowires have n-type dopants.

Abstract: We investigated how surface roughness, intentionally induced by chemical-mechanical polishing, affects the formation of ohmic contacts to an n-type 4H-SiC using a common circular transmission length method (CTLM). Nickel metal was used as the cathode ohmic contacts to n-type SiC. The specific contact resistance (SCR) for the un-polished sample (F1) and polished samples (F2 and F3) was 5.4 × 10-3
⋅cm2 and 4.2 × 10-3
⋅cm2, respectively. We found out that the un-polished sample (F1) had much higher SCR than the samples , F2 and F3. In addition, we did not see any difference between the differently polished samples, F2 and F3, indicating that there was no dependence on the face type of SiC (Si- or C-face) in the values of SCR. We also investigated the die-bonding processes with the surface roughness and metallization schemes' effects.

Abstract: We report on the die bonding processes and how the surface roughness and metallization schemes affect the processes of die bonding in 4H-SiC device fabrication using a soldering test and die shear test (DST) with differently prepared 4H-SiC samples. The first set of samples (FZ#1 and FZ#2) was capped with sequentially evaporated Ti and Au on an annealed Ni layer. The second set of samples (FZ#3 and FZ#4) and the third set of samples (FZ#5 and FZ#6) were prepared by 4μm-thick Au electroplating on an annealed Ni layer and an un-annealed Ni layer, respectively. The quality of the soldering, such as the solder coverage, void, and adhesion, was characterized by optical microscope, X-ray microprobe, and DST. We found that the samples (FZ#4 and FZ#6) deposited by Au electroplating on C-face (bottom-side) 4H-SiC provided a satisfactory result for the tests of solder coverage, void, and DST and also realized the cleaning process prior to the electroplating and soldering was the most crucial in the die packaging processes of vertical structure devices. The void fraction measured by X-ray microprobe for the samples, FZ#4 and FZ#6 was 2.2% (average for 5 samples) and 0.8% (average for 3 samples), respectively.

Abstract: We demonstrate the fabrication and the electrical transport properties of single crystalline 3C silicon carbide nanowires (SiC NWs). The growth of SiC NWs was carried out in a chemical vapor deposition (CVD) furnace. Methyltrichlorosilane (MTS, CH3SiCl3) was chosen as a source precursor. SiC NWs had diameters of less than 100 nm and lengths of several μm. For electrical transport measurements, as-gown SiC NWs were prepared on a highly doped silicon wafer, pre-patterned by a photo-lithography process, with a 400 nm thick SiO2 layer. Source and drain electrodes were defined by e-beam lithography (EBL). Prior to the metal deposition (Ti/Au : 40 nm/70 nm) by thermal evaporation, the native oxide on SiC NWs was removed by buffered HF. The estimated mobility of carriers is 15 cm2/(Vs) for a source-drain voltage (VSD) of 0.02 V. It is very low compared to that expected in bulk and/or thin film 3C-SiC. The electrical measurements from nanowire-based field effect transistor (FET) structures illustrate that SiC NWs are weak n-type semiconductor. We have also demonstrated a powerful technique, a standard UV photo-lithography process, for fabrication of SiC nanowires instead of using EBL process.

Abstract: We report on simple techniques for extracting the electrical properties of 1-dimensional semiconductor nanowires using standard ultraviolet (UV) photo-lithography instead of e-beam lithography (EBL), which is a commonly used technique for the fabrication of nanoscale electrical devices. For electrical transport measurement the gallium nitride nanowires (GaN NWs) were prepared by a horizontal hot-wall chemical vapor deposition (CVD) with metallic Ga and NH3 gas for Ga and N sources, and GaN nanowire field effect transistor (FET) structures on a 8×8 mm2 silicon wafer were fabricated by ordinary 2-mask photo-lithography processes. The estimated carrier mobility from the gate-modulation characteristics is on the order of 60 ∼ 70 cm2/V⋅s. We found that our approach is a powerful and simple technique to extract the electrical properties of semiconductor nanowires. The material characteristics of GaN nanowires are also discussed.